专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2022015800A1 IMAGING SYSTEM INCLUDING ANALOG COMPRESSION FOR SIMULTANEOUS PULSE DETECTION AND IMAGING 审中-公开
公开(公告)号：WO2022015800A1
公开(公告)日：2022-01-20
申请号：PCT/US2021/041551
申请日：2021-07-14
申请人： RAYTHEON COMPANY
发明人： BATINICA, Michael J. , BOEMLER, Christian M. , BRYANT, Paul
IPC分类号： H04N5/3745 , H04N5/355 , H04N5/369
摘要： An imaging system includes a light sensor, a pulse detection imaging (PDI) circuit, and an image processing unit. The light sensor generates one or both of an image signal and a pulse signal. The pulse PDI circuit includes a first terminal in signal communication with the light sensor to receive one or both of the image signal and the pulse signal and a second terminal in signal communication with a voltage source. The image processing unit is in signal communication with the PDI circuit to receive one or both of the image signal and the pulse signal and to simultaneously perform imagery and pulse detection based on the image signal and the pulse signal, respectively.

2. 发明申请

WO2020072180A1 WIDE SUPPLY RANGE DIGITAL LEVEL SHIFTER CELL 审中-公开
公开(公告)号：WO2020072180A1
公开(公告)日：2020-04-09
申请号：PCT/US2019/050525
申请日：2019-09-11
申请人： RAYTHEON COMPANY
发明人： BOEMLER, Christian M.
IPC分类号： H03K3/013 , H03K3/356
摘要： A wide supply range digital level shifter circuit (100) shifts between a variable desired output voltage (160) ranging from a first voltage level (digital high) and a second voltage level (digital low). The wide supply range digital level shifter circuit includes a latch circuit (106), a first bleeder circuit (112), and a second bleeder circuit (114). The latch circuit receives the first voltage level (digital high) and the second voltage level (digital low), and includes first and second clocked differential switches (116, 118). The first bleeder circuit is connected between the second voltage rail (104) and the first differential switch (116) and is configured to receive a first digital input voltage (Clear). The second bleeder circuit is connected between the second voltage rail and the second differential switch (118) and is configured to receive a second digital input voltage (Set). The first and second bleeder circuits isolate (though 117, 119) the first and second digital input voltages (at gates of 116, 118) from the variable desired output voltage (160).

3. 发明申请

WO2020180558A1 LOW NOISE PASSIVE PIXEL READOUT CIRCUIT 审中-公开
公开(公告)号：WO2020180558A1
公开(公告)日：2020-09-10
申请号：PCT/US2020/019877
申请日：2020-02-26
申请人： RAYTHEON COMPANY
发明人： BOEMLER, Christian M.
IPC分类号： H04N5/3745 , H04N5/378 , H04N5/365 , H04N5/357
摘要： A passive readout circuit for reading out a charge stored on an integration capacitor coupled to a photodiode includes a column bus selectively connectable to the integration capacitor, at least one shield line arranged near the column bus such that a first parasitic capacitance is created between the at least one shield line and the column bus and an amplifier having a first input, a second input and an output. The column is connected to the first input and the at least one shield line is connected to the output of the amplifier.

4. 发明申请

WO2018075445A1 SELF-RECOVERING DIGITAL LATCH 审中-公开
标题翻译：自我恢复数字锁
公开(公告)号：WO2018075445A1
公开(公告)日：2018-04-26
申请号：PCT/US2017/056876
申请日：2017-10-17
申请人： RAYTHEON COMPANY
发明人： BOEMLER, Christian M.
IPC分类号： G11C5/00 , H03K3/0233 , G06F11/10 , H03K19/003 , G11C11/412 , H04N5/33
摘要： An electro-optical sensor chip assembly (SCA) that includes a detection device that includes an array of detector unit cells arranged in a matrix and that produce an electrical output in response to light. The SCA also includes an integrated control circuit in electrical communication with the detection device that includes a control word store to store a dataword. The control word store includes at least three sub-latches to redundantly store at least one bit of the dataword. The at least three sub-latches include a first sub-latch, a second sub-latch and a third sub-latch, each of the first sub-latch, the second sub-latch and the third sub-latch including an output and two recovery inputs, and the output of the first and third sub-latches are connected to the recovery inputs of the second sub-latch.
摘要翻译：包括检测装置的电光传感器芯片组件（SCA）包括布置成矩阵的检测器单元阵列的阵列并且响应于光而产生电输出。 SCA还包括与检测装置电通信的集成控制电路，其包括用于存储数据字的控制字存储器。控制字存储器包括至少三个子锁存器以冗余地存储数据字的至少一个比特。所述至少三个子锁存器包括第一子锁存器，第二子锁存器和第三子锁存器，第一子锁存器，第二子锁存器和第三子锁存器中的每一个包括输出和两个恢复输入，并且第一和第三子锁存器的输出端连接到第二子锁存器的恢复输入端。

5. 发明申请

WO2013158965A1 REPARTITIONED DIGITAL PIXEL 审中-公开
标题翻译：数位数字像素
公开(公告)号：WO2013158965A1
公开(公告)日：2013-10-24
申请号：PCT/US2013/037319
申请日：2013-04-19
申请人： RAYTHEON COMPANY
发明人： DENHAM, Martin, S. , BOEMLER, Christian M.
IPC分类号： H04N5/3745
CPC分类号： H04N5/347 , H04N5/37455 , Y10T29/49128
摘要： An imaging system includes an array of pixel cells and a plurality of digital memory elements disposed physically separate from and coupled to the array of pixel cells. Each of the pixel cells includes a photodetector, an electrical storage device coupled to the photodetector, and quantization circuitry coupled to the electrical storage device. The photodetector is configured to generate a photo-current in response to light impinging thereon. The electrical storage device is configured to accumulate an electrical charge from the photo-current. The quantization circuitry is configured to convert the electrical charge into an analog quantization event signal. Each of the digital memory elements is in electrical communication with at least one of the pixel cells and is configured to store a digital value in response to receiving the analog quantization event signal from the at least one of the pixel cells.
摘要翻译：成像系统包括像素单元阵列和与像素单元阵列物理分离并耦合到像素单元阵列的多个数字存储器元件。每个像素单元包括光电检测器，耦合到光电检测器的电存储器件，以及耦合到电存储器件的量化电路。光电检测器被配置为响应于其上的光照射而产生光电流。电存储装置被配置为从光电流累积电荷。量化电路被配置为将电荷转换成模拟量化事件信号。每个数字存储器元件与像素单元中的至少一个电气通信，并且被配置为响应于从至少一个像素单元接收模拟量化事件信号来存储数字值。

6. 发明申请

WO2020072584A1 PUMPED LARGE FULL WELL PIXEL 审中-公开
公开(公告)号：WO2020072584A1
公开(公告)日：2020-04-09
申请号：PCT/US2019/054203
申请日：2019-10-02
申请人： RAYTHEON COMPANY
发明人： BOEMLER, Christian M.
IPC分类号： H04N5/3745 , H04N5/355
摘要： A pixel includes an integration capacitor coupled between a system voltage and a pump voltage source and having a first side and a second side. The pixel can be operated to have a large full well by: storing charge from a photo-current source in the integration capacitor; reading out the integration capacitor; resetting the integration capacitor by connecting the capacitor to a column line through a select transistor; while resetting, setting the pump voltage source to the system voltage; and after resetting, setting the pump voltage to ground to create a negative voltage between the integration capacitor and column line.

7. 发明申请

WO2020041651A1 PER-PIXEL DETECTOR BIAS CONTROL 审中-公开
公开(公告)号：WO2020041651A1
公开(公告)日：2020-02-27
申请号：PCT/US2019/047810
申请日：2019-08-23
申请人： RAYTHEON COMPANY
发明人： BEUVILLE, Eric J. , HARRIS, Micky , BOESCH, Ryan , BOEMLER, Christian M.
IPC分类号： H04N5/365 , H04N5/3745 , H01L27/146 , H01L29/792
摘要： A pixel includes a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and an injection transistor disposed between the photo-diode and the integration capacitor that controls flow of the photo current from the photo-diode to the integration capacitor, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor. The injection transistor is a siliconoxidenitrideoxidesilicon (SONOS) FET having its gate set to a SONOS gate voltage to control a detector bias voltage of the photo-diode at the first node.

8. 发明申请

WO2018175562A1 LOW POWER ANALOG-TO-DIGITAL CONVERTER 审中-公开
公开(公告)号：WO2018175562A1
公开(公告)日：2018-09-27
申请号：PCT/US2018/023537
申请日：2018-03-21
申请人： RAYTHEON COMPANY
发明人： BOEMLER, Christian M.
IPC分类号： H03M1/08 , H03M1/56
摘要： A single slope analog to digital converter includes a comparator having a positive input and a negative input and a comparator output, a counter and a latch connected to an output of the counter and that includes a trigger input. Also included is a pulse generator coupled to the comparator output that produces a pulse of a defined width each time a signal on the negative input transitions from a voltage level that is below a voltage level on the positive input to a voltage level that is above the voltage level on the positive input.

9. 发明申请

WO2020072581A1 AUTOZERO OF BUFFERED DIRECT INJECTION PIXELS 审中-公开
公开(公告)号：WO2020072581A1
公开(公告)日：2020-04-09
申请号：PCT/US2019/054200
申请日：2019-10-02
申请人： RAYTHEON COMPANY
发明人： BOEMLER, Christian M.
IPC分类号： H04N5/3745 , H04N5/365
摘要： A buffered direct injection pixel can be operated such that is automatically zeroed. The operation includes: during a normal operating mode, controlling a gate voltage of an injection transistor with the output of an amplifier to control a bias of photo-current source, an inverting input of the amplifier being connected to input of the injection transistor through a nulling capacitor; during a nulling operation, closing a first switch to connect the nulling capacitor directly to an output of the amplifier; during the nulling operation, closing a second switch to directly couple the input of the injection transistor to a bias voltage causing the nulling capacitor to store a difference between an output of the amplifier and the bias voltage; and after the nulling operation, providing the voltage stored on the nulling capacitor to the inverting input by opening the first and second switches.

10. 发明申请

WO2020072347A1 SELF-CORRECTING ANALOG COUNTER READOUT FOR DIGITAL PIXELS 审中-公开
公开(公告)号：WO2020072347A1
公开(公告)日：2020-04-09
申请号：PCT/US2019/053773
申请日：2019-09-30
申请人： RAYTHEON COMPANY
发明人： BOEMLER, Christian M.
IPC分类号： H04N5/3745 , H04N5/378
摘要： A digital unit cell, readout circuit for a digital unit cell and a method of operating an analog counter of a digital unit cell is disclosed. The readout circuit includes storage capacitor for storing a voltage remaining at an analog counter at the end of an integration period, and a comparator circuit. The comparator circuit compares a dummy voltage provided from the analog counter during a readout period to the voltage at the storage capacitor, and determines the voltage at the storage capacitor when the dummy voltage falls below the voltage at the storage capacitor.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式