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1. 发明申请

WO03003885A3 SECURITY LETTERBOX ASSEMBLY 审中-公开
标题翻译：安全信纸总成
公开(公告)号：WO03003885A3
公开(公告)日：2003-04-24
申请号：PCT/GB0202502
申请日：2002-05-28
申请人： RABINOVITCH ALEXANDER , RABINOVITCH EFIM
发明人： RABINOVITCH ALEXANDER , RABINOVITCH EFIM
IPC分类号： A47G29/124 , A47G29/122
CPC分类号： A47G29/124
摘要： A security letterbox assembly comprises a watertight body (1), a letter plate (4), a delivery flap (5), an adjustable mail protection means (6) and a mail detention means (11,12,14). The mail protection means may include three plates held by two axles, where at least one axle is spring loaded and is designed to prevent mail being removed from the body, whilst moving towards the body to allow mail to be inserted into the body. The mail detention means may be in the form of a downwardly urged jagged edged flap (11) and jagged edged mail retention means (14), between which the mail is detained. A watertight means (9) is located between the body and structure (3) and in a further aspect of the invention is flexible to maintain a seal when the body is moved away from the structure. The body is adjustably secured to the structure and letter plate by fixing means (19, 24-26).
摘要翻译：安全信箱组件包括防水体（1），字母板（4），输送片（5），可调邮件保护装置（6）和邮件扣留装置（11,12,14）。邮件保护装置可以包括由两个轴保持的三个板，其中至少一个轴被弹簧加载，并被设计成防止邮件从身体移除，同时向身体移动以允许邮件插入到身体中。邮件拘留装置可以是向下推动的锯齿边缘（11）和锯齿状边缘邮件保留装置（14）的形式，邮件被扣留在其间。水密装置（9）位于主体和结构（3）之间，并且在本发明的另一方面，当身体远离结构移动时，柔性可保持密封。主体通过固定装置（19,24-26）可调节地固定在结构和字母板上。

2. 发明申请

WO2010126683A2 LOGIC SIMULATION AND/OR EMULATION WHICH FOLLOWS HARDWARE SEMANTICS 审中-公开
标题翻译：跟踪硬件语义的逻辑仿真和/或仿真
公开(公告)号：WO2010126683A2
公开(公告)日：2010-11-04
申请号：PCT/US2010030163
申请日：2010-04-07
申请人： SYNOPSYS INC , RABINOVITCH ALEXANDER , NARAYANASWAMY RAMESH
发明人： RABINOVITCH ALEXANDER , NARAYANASWAMY RAMESH
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022
摘要： Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation.
摘要翻译：本发明的一些实施例提供了用于模拟电路设计的技术和系统，使得仿真遵循硬件语义。具体地，一些实施例确保仿真遵循硬件语义，通过适当地处理可能在逻辑模拟期间发生的时钟树中的状态元素和/或毛刺中的竞争条件。每个逻辑模拟循环可以包括两个阶段：系统评估不依赖于时钟信号的电路设计的信号值的刺激应用阶段以及系统评估依赖于时钟的信号值的时钟传播阶段信号。本发明的一些实施例在刺激应用阶段期间采样信号值，并且在时钟传播阶段期间使用采样信号值来处理可能在逻辑模拟期间发生的时钟树中的状态元件和/或毛刺中的竞争条件。

3. 发明申请

WO2009123828A3 COMPACT CIRCUIT-SIMULATION OUTPUT 审中-公开
标题翻译：紧凑的电路 - 模拟输出
公开(公告)号：WO2009123828A3
公开(公告)日：2009-11-26
申请号：PCT/US2009036495
申请日：2009-03-09
申请人： SYNOPSYS INC , RABINOVITCH ALEXANDER , SHROFF MANISH
发明人： RABINOVITCH ALEXANDER , SHROFF MANISH
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： Embodiments of a computer system for simulating a circuit are described. During a first mode of the simulation, the computer system stores primary signals and circuit relationships between primary signals and secondary signals associated with a portion of the circuit in a file, where the primary signals are independent of gate outputs in the portion of the circuit, and the secondary signals are driven by gates in the portion of the circuit. Moreover, during a second mode of the simulation, the computer system stores dynamic changes in additional relationships between signals to the file, where the signals can include primary signals, secondary signals, or both.
摘要翻译：描述用于模拟电路的计算机系统的实施例。在模拟的第一模式期间，计算机系统存储与文件中的电路的一部分相关联的主信号和次级信号之间的主信号和电路关系，其中主信号独立于电路的该部分中的栅极输出，并且次级信号由电路部分中的门驱动。此外，在模拟的第二模式期间，计算机系统在信号到文件的附加关系中存储动态变化，其中信号可以包括主信号，次信号或两者。

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