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1. 发明申请

WO2010127168A1 DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION USING AN ACCUMULATOR AND A PHASE-TO-DIGITAL CONVERTER 审中-公开
标题翻译：使用累加器和相数转换器进行两点调制的数字锁相环
公开(公告)号：WO2010127168A1
公开(公告)日：2010-11-04
申请号：PCT/US2010/033044
申请日：2010-04-29
申请人： QUALCOMM INCORPORATED , GENG, Jifeng , BALLANTYNE, Gary John , FILIPOVIC, Daniel F.
发明人： GENG, Jifeng , BALLANTYNE, Gary John , FILIPOVIC, Daniel F.
IPC分类号： H03C3/09
CPC分类号： H03L7/089 , H03C3/0916 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L7/085
摘要： A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.
摘要翻译：描述了支持两点调制的数字锁相环（DPLL）。在一种设计中，DPLL包括一个相位数转换器和一个环路工作的环路滤波器，一个用于低通调制路径的第一处理单元和一个用于高通调制路径的第二处理单元。第一处理单元接收输入调制信号，并且在相位数转换器之后并且在环路滤波器之前向环路内的第一点提供第一调制信号。第二处理单元接收输入的调制信号，并且在环路滤波器之后向环路内的第二点提供第二调制信号。第一处理单元可以包括累积输入调制信号以将频率转换为相位的累加器。第二处理单元可以包括用可变增益来缩放输入调制信号的缩放单元。

2. 发明申请

WO2010068679A2 DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION AND ADAPTIVE DELAY MATCHING 审中-公开
标题翻译：具有两点调制和自适应延迟匹配的数字相位锁定环
公开(公告)号：WO2010068679A2
公开(公告)日：2010-06-17
申请号：PCT/US2009/067354
申请日：2009-12-09
申请人： QUALCOMM Incorporated , GENG, Jifeng , BALLANTYNE, Gary, John , FILIPOVIC, Daniel, F.
发明人： GENG, Jifeng , BALLANTYNE, Gary, John , FILIPOVIC, Daniel, F.
IPC分类号： H03L7/06
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0966
摘要： A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay.
摘要翻译：描述了支持具有自适应延迟匹配的两点调制的数字锁相环（DPLL）。 DPLL包括分别支持振荡器的频率和/或相位的宽带和窄带调制的高通和低通调制路径。 DPLL可以自适应地调整一个调制路径的延迟以匹配另一个调制路径的延迟。在一种设计中，DPLL包括为两个调制路径中的一个提供可变延迟的自适应延迟单元。在自适应延迟单元内，延迟计算单元基于施加到两个调制路径的调制信号和DPLL中的相位误差信号来确定可变延迟。内插器提供可变延迟的小数部分，并且可编程延迟单元提供可变延迟的整数部分。

3. 发明申请

WO2010144912A1 PLL DISTURBANCE CANCELLATION 审中-公开
标题翻译： PLL干扰消除
公开(公告)号：WO2010144912A1
公开(公告)日：2010-12-16
申请号：PCT/US2010/038531
申请日：2010-06-14
申请人： QUALCOMM Incorporated , FILIPOVIC, Daniel F. , BALLANTYNE, Gary John , GENG, Jifeng
发明人： FILIPOVIC, Daniel F. , BALLANTYNE, Gary John , GENG, Jifeng
IPC分类号： H03L7/093
CPC分类号： H03L7/093
摘要： Techniques for cancelling a disturbance signal from a PLL output signal. In an aspect, a cancellation signal is combined with the signal input to a VCO or DCO in the PLL. In a further aspect, the appropriate cancellation signal is derived by analyzing one or more signals within the PLL. The signals within the PLL may be correlated against one or more disturbance signal templates, such as a sinusoid having a known frequency, to derive one or more correlation coefficients. The coefficients may be applied to weight one or more disturbance synthesis functions to generate the cancellation signal. Further aspects provide for joint analysis, synthesis, and cancellation of signals having unknown frequency from the PLL output.
摘要翻译：从PLL输出信号中消除干扰信号的技术。在一方面，消除信号与输入到PLL中的VCO或DCO的信号组合。在另一方面，通过分析PLL内的一个或多个信号来导出适当的抵消信号。 PLL内的信号可以与一个或多个干扰信号模板（例如具有已知频率的正弦波）相关，以导出一个或多个相关系数。可以应用系数来加权一个或多个干扰合成功能以产生消除信号。其他方面提供了从PLL输出端对未知频率的信号的联合分析，合成和消除。

4. 发明申请

WO2010141909A1 DIGITAL PHASE LOCKED LOOP WITH PARTS OPERATING AT DIFFERENT SAMPLE RATES 审中-公开
标题翻译：数字相位锁定环与不同采样率的零件操作
公开(公告)号：WO2010141909A1
公开(公告)日：2010-12-09
申请号：PCT/US2010/037530
申请日：2010-06-04
申请人： QUALCOMM Incorporated , BALLANTYNE, Gary, John , GENG, Jifeng , FILIPOVIC, Daniel, F.
发明人： BALLANTYNE, Gary, John , GENG, Jifeng , FILIPOVIC, Daniel, F.
IPC分类号： H03L7/08 , H03C3/09
CPC分类号： H03L7/08 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L2207/50
摘要： A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a DCO output signal and a reference clock and outputs a first stream of digital values. Quantization noise is reduced by clocking the TDC at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate, thereby reducing digital images. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate, thereby further reducing power consumption.
摘要翻译：数字锁相环（DPLL）涉及一个时间数字转换器（TDC），它接收DCO输出信号和参考时钟并输出第一个数字值。通过以较高的速率计时TDC来减少量化噪声。下采样电路将第一流转换为第二流。第二流被提供给DPLL的相位检测加法器，使得DPLL的控制部分可以以较低的速率切换以降低功耗。因此，DPLL被称为多速率DPLL。由控制部分输出的第三个数字调谐字流在被提供给DCO之前被上采样，从而可以以更高的速率计时DCO，从而减少数字图像。在接收机应用中，不执行上采样，并且以较低的速率对DCO进行计时，从而进一步降低功耗。

5. 发明申请

WO2010033853A1 ADAPTIVE CALIBRATION FOR DIGITAL PHASE-LOCKED LOOPS 审中-公开
标题翻译：数字相位锁定自适应校准
公开(公告)号：WO2010033853A1
公开(公告)日：2010-03-25
申请号：PCT/US2009/057550
申请日：2009-09-18
申请人： QUALCOMM Incorporated , GENG, Jifeng , FILIPOVIC, Daniel F. , KOMNINAKIS, Christos
发明人： GENG, Jifeng , FILIPOVIC, Daniel F. , KOMNINAKIS, Christos
IPC分类号： H03L7/091
CPC分类号： H03L7/091 , H03L2207/50
摘要： Techniques for adaptively calibrating a TDC output signal in a digital phase-locked loop (DPLL). In an exemplary embodiment, a calibration factor multiplied to the TDC output signal is adaptively adjusted to minimize a magnitude function of a phase comparator output signal of the DPLL. In an exemplary embodiment, the calibration factor may be adjusted using an exemplary embodiment of the least-mean squares (LMS) algorithm. Further techniques for simplifying the adaptive algorithm for hardware implementation are described.
摘要翻译：用于在数字锁相环（DPLL）中自适应校准TDC输出信号的技术。在示例性实施例中，自适应地调整与TDC输出信号相乘的校准因子，以最小化DPLL的相位比较器输出信号的幅度函数。在示例性实施例中，可以使用最小均方（LMS）算法的示例性实施例来调整校准因子。描述了用于简化用于硬件实现的自适应算法的进一步的技术。

6. 发明申请

WO2011084527A3 SIGNAL DECIMATION TECHNIQUES BASED ON A CONFIGURABLE FREQUENCY DIVIDER AND A CONFIGURABLE DELAY 审中-公开
公开(公告)号：WO2011084527A3
公开(公告)日：2011-07-14
申请号：PCT/US2010/060585
申请日：2010-12-15
申请人： QUALCOMM INCORPORATED , BALLANTYNE, Gary John , GENG, Jifeng , SUN, Bo
发明人： BALLANTYNE, Gary John , GENG, Jifeng , SUN, Bo
IPC分类号： H03B19/00 , H03D7/16 , G06F1/08 , H03L7/00 , H04B1/00
摘要： Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.

7. 发明申请

WO2012097358A1 IMPLEMENTATIONS FOR WIRELESS SIGNAL PROCESSING 审中-公开
标题翻译：无线信号处理的实现
公开(公告)号：WO2012097358A1
公开(公告)日：2012-07-19
申请号：PCT/US2012/021434
申请日：2012-01-16
申请人： QUALCOMM INCORPORATED , FILIPOVIC, Daniel, F. , GENG, Jifeng
发明人： FILIPOVIC, Daniel, F. , GENG, Jifeng
IPC分类号： G01S19/30 , G01S19/29 , G01S19/09
CPC分类号： G01S19/09
摘要： Implementations including methods, apparatuses, and systems relating to processing wireless signals are disclosed. Such processing may be performed, at least in part, at a receiver platform receiving such wireless signals and/or at a remote computing platform to obtain information that may be used in a variety of contexts, including cellular communications, radio-frequency identification, and navigation. In some techniques, modulated signals are received at a receiver platform, and at least partially demodulated and used to generate data. The data is transmitted to one or more network resources, and processed to obtain information based on the information in the modulated signals.
摘要翻译：公开了包括与处理无线信号有关的方法，装置和系统的实现。这种处理可以至少部分地在接收这样的无线信号的接收机平台上和/或在远程计算平台上执行，以获得可以在各种上下文中使用的信息，包括蜂窝通信，射频识别和导航。在一些技术中，在接收器平台处接收调制信号，并且至少部分解调并用于产生数据。将数据发送到一个或多个网络资源，并根据调制信号中的信息进行处理以获得信息。

8. 发明申请

WO2012078818A1 METHOD AND APPARATUS FOR FREQUENCY SYNTHESIZING 审中-公开
标题翻译：用于频率合成的方法和装置
公开(公告)号：WO2012078818A1
公开(公告)日：2012-06-14
申请号：PCT/US2011/063843
申请日：2011-12-07
申请人： QUALCOMM INCORPORATED , BO, Sun , GENG, Jifeng
发明人： BO, Sun , GENG, Jifeng
IPC分类号： H03K5/135 , H03K5/156 , H03L7/08
CPC分类号： H03K5/135 , H03K5/1565 , H03L7/0816 , H03L7/16
摘要： Systems and methods for frequency synthesis are disclosed. Exemplary embodiments of the digital frequency synthesizer (105) can produce a fixed frequency and/or a modulated signal (130). An exemplary digital frequency synthesizer includes series - coupled delay cells (210), a linear feedback shift register (225), and an accumulator (275). The series - coupled delay cells (210) generate, from an input clock signal (125), multiple clock edges (205) corresponding to fractional clock periods. A linear feedback shift register (225) selects clock edges to pass to a combinational logic circuit (255), based on a sign/enable control signal (230) received from an accumulator (275) and a clock signal (240) received from the combinational logic circuit's output (240). The accumulator (275) receives a control signal (280) and controls the phase of the synthesizer output (130) based upon the received control signal (280).
摘要翻译：公开了用于频率合成的系统和方法。数字频率合成器（105）的示例性实施例可以产生固定频率和/或调制信号（130）。示例性数字频率合成器包括串联耦合延迟单元（210），线性反馈移位寄存器（225）和累加器（275）。串联耦合延迟单元（210）从输入时钟信号（125）产生对应于分数时钟周期的多个时钟边沿（205）。线性反馈移位寄存器（225）基于从累加器（275）接收的符号/使能控制信号（230）和从接收到的累加器（275）接收的时钟信号（240），选择要传递到组合逻辑电路（255）的时钟边沿组合逻辑电路的输出（240）。累加器（275）接收控制信号（280），并基于所接收的控制信号（280）控制合成器输出（130）的相位。

9. 发明申请

WO2013040505A1 CIRCUITRY FOR REDUCING POWER CONSUMPTION 审中-公开
标题翻译：降低功耗的电路
公开(公告)号：WO2013040505A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/055642
申请日：2012-09-14
申请人： QUALCOMM INCORPORATED , KOMNINAKIS, Christos , CHELLAPPA, Vijay K. , GENG, Jifeng
发明人： KOMNINAKIS, Christos , CHELLAPPA, Vijay K. , GENG, Jifeng
IPC分类号： H03F1/02 , H03F1/32 , H03F3/24
CPC分类号： H03F1/3241 , H03F1/0244 , H03F1/0266 , H03F1/0272 , H03F1/3247 , H03F3/24 , H03F2200/321 , H03F2201/3233 , H04B2001/0408 , H04L25/03343
摘要： Circuitry (102) for reducing power consumption is described. The circuitry (102) includes a power amplifier (110). The circuitry (102) also includes a predistorter (106) coupled to the power amplifier (110). The circuitry (102) further includes a power supply (116) coupled to the power amplifier (110). The circuitry (102) additionally includes a controller (122) coupled to the power amplifier (110), to the predistorter (106) and to the power supply (116). The controller (122) captures a transmit signal (104b) and a feedback signal (112) concurrently and determines a minimum bias voltage from a set of voltages and a predistortion that enable the power amplifier (110) to produce an amplified transmit signal (108) in accordance with a requirement.
摘要翻译：描述了用于降低功耗的电路（102）。电路（102）包括功率放大器（110）。电路（102）还包括耦合到功率放大器（110）的预失真器（106）。电路（102）还包括耦合到功率放大器（110）的电源（116）。电路（102）还包括耦合到功率放大器（110），预失真器（106）和电源（116）的控制器（122）。控制器（122）同时捕获发射信号（104b）和反馈信号（112），并从一组电压和预失真确定最小偏置电压，使得功率放大器（110）能够产生放大的发射信号（108 ）根据要求。

10. 发明申请

WO2011071953A1 PHASE LOCKED LOOP WITH DIGITAL COMPENSATION FOR ANALOG INTEGRATION 审中-公开
标题翻译：用于模拟集成的数字补偿的相位锁定环
公开(公告)号：WO2011071953A1
公开(公告)日：2011-06-16
申请号：PCT/US2010/059337
申请日：2010-12-07
申请人： QUALCOMM Incorporated , DUNWORTH, Jeremy D. , BALLANTYNE, Gary J. , ASURI, Bhushan S. , GENG, Jifeng , SAHOTA, Gurkanwal S.
发明人： DUNWORTH, Jeremy D. , BALLANTYNE, Gary J. , ASURI, Bhushan S. , GENG, Jifeng , SAHOTA, Gurkanwal S.
IPC分类号： H03L7/093
CPC分类号： H03L7/08 , H03L7/093
摘要： A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal, The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).
摘要翻译：锁相环（PLL）装置包括数字微分器，其被配置为区分数字环路信号以至少部分地补偿模拟积分器对模拟电流信号的积分。数模转换器（DAC）包括基于数字输入信号产生模拟电流信号的电流源输出级。模拟积分器对模拟电流信号进行积分以产生用于控制压控振荡器（VCO）的电压控制信号，。

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