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1. 发明申请

WO2017172205A1 IDENTIFYING ENHANCED SYNCHRONIZATION OPERATION OUTCOMES TO IMPROVE RUNTIME OPERATIONS 审中-公开
标题翻译：识别增强的同步操作结果以改善运行时间操作
公开(公告)号：WO2017172205A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/020164
申请日：2017-03-01
申请人： QUALCOMM INCORPORATED
发明人： SUAREZ GRACIA, Dario , CASCAVAL, Gheorghe , ZHAO, Han , KUMAR, Tushar , NATARAJAN, Aravind , RAMAN, Arun
IPC分类号： G06F9/52
CPC分类号： G06F9/52 , G06F9/46
摘要： Embodiments include computing devices, systems, and methods identifying enhanced synchronization operation outcomes. A computing device may receive a first resource access request for a first resource of a computing device including a first requester identifier from a first computing element of the computing device. The computing device may also receive a second resource access request for the first resource including a second requester identifier from a second computing element of the computing device. The computing device may grant the first computing element access to the first resource based on the first resource access request, and return a response to the second computing element including the first requester identifier as a winner computing element identifier.
摘要翻译：实施例包括识别增强的同步操作结果的计算设备，系统和方法。计算设备可以从计算设备的第一计算元件接收针对包括第一请求者标识符的计算设备的第一资源的第一资源访问请求。计算设备还可以从计算设备的第二计算元件接收针对包括第二请求者标识符的第一资源的第二资源访问请求。计算设备可以基于第一资源访问请求向第一计算元件授予对第一资源的访问权，并且向第二计算元件返回包括第一请求者标识符的响应作为获胜者计算元件标识符。

2. 发明申请

WO2016014236A1 METHODS AND SYSTEMS FOR DETECTING MALWARE AND ATTACKS THAT TARGET BEHAVIORAL SECURITY MECHANISMS OF A MOBILE DEVICE 审中-公开
标题翻译：用于检测恶意软件的方法和系统和攻击目标移动设备的行为安全机制
公开(公告)号：WO2016014236A1
公开(公告)日：2016-01-28
申请号：PCT/US2015/039288
申请日：2015-07-07
申请人： QUALCOMM INCORPORATED
发明人： SUAREZ GRACIA, Dario , GUPTA, Rajarshi , GANTMAN, Alexander
IPC分类号： G06F21/56 , H04L29/06 , G06F21/57 , H04W24/06 , H04W12/12
CPC分类号： H04W12/10 , G06F21/561 , G06F21/566 , G06F21/577 , G06F2221/033 , H04L63/1416 , H04L63/1433 , H04W12/12 , H04W24/06
摘要： A behavior-based security system of a computing device may be protected from non-benign behavior, malware, and cyber attacks by configuring the device to work in conjunction with another component (e.g., a server) to monitor the accuracy and performance of the security system, and determine whether the system is working correctly, efficiently, or as expected. This may be accomplished via the server generating artificial attack software, sending the generated artificial attack software to the mobile device to simulate non-benign behavior in the mobile device, such as a cyber attack, and determining whether the behavior-based security system of the mobile device responded adequately to the simulated non-benign behavior. The sever may send a dead-man signal to the mobile device in response to determining that the behavior-based security system of the mobile device did not respond adequately to the simulated non-benign behavior.
摘要翻译：计算设备的基于行为的安全系统可以通过将该设备与另一个组件（例如，服务器）配合工作来监视安全性的准确性和性能，从而防止非良性行为，恶意软件和网络攻击系统，并确定系统是否正常，有效或正常工作。这可以通过产生人造攻击软件的服务器来实现，将生成的人造攻击软件发送到移动设备以模拟移动设备中的非良性行为，例如网络攻击，以及确定是否基于行为的安全系统移动设备对模拟的非良性行为作出了充分的反应。响应于确定移动设备的基于行为的安全系统对模拟的非良性行为没有充分响应，服务器可以向移动设备发送死人信号。

3. 发明申请

WO2017127180A1 RANDOM-ACCESS DISJOINT CONCURRENT SPARSE WRITES TO HETEROGENEOUS BUFFERS 审中-公开
标题翻译：随机访问异步并发向异构缓冲区写入
公开(公告)号：WO2017127180A1
公开(公告)日：2017-07-27
申请号：PCT/US2016/066319
申请日：2016-12-13
申请人： QUALCOMM INCORPORATED
发明人： KUMAR, Tushar , NATARAJAN, Aravind , SUAREZ GRACIA, Dario
IPC分类号： G06F9/46
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0673 , G06F9/3834 , G06F9/467 , G06F9/544 , G06F12/1072 , G06F2212/65
摘要： Methods, devices, and non-transitory processor-readable storage media for a computing device to merge concurrent writes from a plurality of processing units to a buffer associated with an application. An embodiment method executed by a processor may include identifying a plurality of concurrent requests to access the buffer that are sparse, disjoint, and write-only, configuring a write-set for each of the plurality of processing units, executing the plurality of concurrent requests to access the buffer using the write-sets, determining whether each of the plurality of concurrent requests to access the buffer is complete, obtaining a buffer index and data via the write-set of each of the plurality of processing units, and writing to the buffer using the received buffer index and data via the write-set of each of the plurality of processing units in response to determining that each of the plurality of concurrent requests to access the buffer is complete.
摘要翻译：用于计算设备的方法，设备和非暂时性处理器可读存储介质将来自多个处理单元的并发写入合并到与应用相关联的缓冲区。由处理器执行的实施例方法可以包括：识别访问缓冲区的多个并发请求，所述并发请求是稀疏的，不相交的和只写的;为多个处理单元中的每一个配置写集;执行多个并发请求使用所述写入集访问所述缓冲器，确定所述多个访问所述缓冲器的并发请求中的每一个是否完成，经由所述多个处理单元中的每一个的所述写入集获得缓冲器索引和数据，以及写入响应于确定访问缓冲器的多个并发请求中的每一个都完成，使用所接收的缓冲器索引和数据经由多个处理单元中的每一个的写入集合来缓冲所述缓冲器。

4. 发明申请

WO2016022308A2 DIRECTED EVENT SIGNALING FOR MULTIPROCESSOR SYSTEMS 审中-公开
标题翻译：针对多处理器系统的指示事件信号
公开(公告)号：WO2016022308A2
公开(公告)日：2016-02-11
申请号：PCT/US2015/042026
申请日：2015-07-24
申请人： QUALCOMM INCORPORATED
发明人： SUAREZ GRACIA, Dario , ZHAO, Han , MONTESINOS ORTEGO, Pablo , CASCAVAL, Gheorghe Calin , XENIDIS, James
IPC分类号： G06F9/52
CPC分类号： G06F1/3296 , G06F9/4856 , G06F9/4893 , G06F9/526 , Y02D10/24
摘要： Multi-processor computing device methods manage resource accesses by a signaling event manager signaling processor elements requesting access to a resource to wake up to access the resource when the resource is available or wait for an event when the resource is busy. Processor elements may enter a sleep state while awaiting access to the requested resource. When multiple elements are waiting for the resource, the processor element with a highest assigned priority is signaled to wake up when the resource is available without waking other elements. Priorities may be assigned to processor elements waiting for the resource based on a heuristic or parameter that may depend on a state of the computing device or the processor elements. A sleep duration may be estimated for a processor element waiting for a resource and the processor element may be removed from a scheduling queue or assigned another thread during the sleep duration.
摘要翻译：多处理器计算设备方法通过信令事件管理器信令处理器元件管理资源访问，所述信令处理器元件在资源可用时请求访问资源以唤醒资源以访问资源，或在资源占用时等待事件。处理器元件可以在等待访问所请求的资源的同时进入休眠状态。当多个元素正在等待资源时，具有最高分配优先级的处理器元件发出信号，以在资源可用时唤醒，而不唤醒其他元素。可以基于可能依赖于计算设备或处理器元件的状态的启发式或参数将优先级分配给等待资源的处理器元件。可以为等待资源的处理器元件估计睡眠持续时间，并且可以在睡眠持续时间期间将处理器元件从调度队列中移除或分配另一个线程。

5. 发明申请

WO2017034738A1 DATA MANAGEMENT FOR MULTIPLE PROCESSING UNITS USING DATA TRANSFER COSTS 审中-公开
标题翻译：使用数据传输成本的多个处理单元的数据管理
公开(公告)号：WO2017034738A1
公开(公告)日：2017-03-02
申请号：PCT/US2016/044168
申请日：2016-07-27
申请人： QUALCOMM INCORPORATED
发明人： SUAREZ GRACIA, Dario , KUMAR, Tushar , NATARAJAN, Aravind , HASTANTRAM, Ravish , CASCAVAL, Gheorghe Calin , ZHAO, Han
IPC分类号： G06F9/50 , G06F9/48 , G06F11/34 , G06F12/0862 , G06F12/12 , G06F12/0806
CPC分类号： G06F9/48 , G06F9/4806 , G06F9/4831 , G06F9/4837 , G06F9/4843 , G06F9/4881 , G06F9/4893 , G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5016 , G06F9/5022 , G06F9/5027 , G06F9/5033 , G06F9/5038 , G06F9/5044 , G06F9/505 , G06F9/5055 , G06F9/5083 , G06F9/5094 , G06F11/3419 , G06F11/3466 , G06F12/0806 , G06F12/0862 , G06F12/12 , G06F12/128 , G06F2212/1016 , G06F2212/62 , Y02D10/22 , Y02D10/24
摘要： Various embodiments include methods for data management in a computing device utilizing a plurality of processing units. Embodiment methods may include generating a data transfer heuristic model based on measurements from a plurality of sample data transfers between a plurality of data storage units. The generated data transfer heuristic model may be used to calculate data transfer costs for each of a plurality of tasks. The calculated data transfer costs may be used to schedule execution of the plurality of tasks in an execution order on selected ones of the plurality of processing units. The data transfer heuristic model may be updated based on measurements of data transfers occurring during the executions of the plurality of tasks (e.g., time, power consumption, etc.). Code executing on the processing units may indicate to a runtime when certain data blocks are no longer needed and thus may be evicted and/or pre-fetched for others.
摘要翻译：各种实施例包括利用多个处理单元的计算设备中的数据管理方法。实施方式可以包括基于来自多个数据存储单元之间的多个采样数据传输的测量来生成数据传输启发式模型。生成的数据传输启发式模型可用于计算多个任务中的每一个的数据传输成本。所计算的数据传输成本可以用于以多个处理单元中的选定的处理单元的执行顺序调度多个任务的执行。可以基于在执行多个任务期间发生的数据传输的测量（例如，时间，功耗等）来更新数据传输启发式模型。在处理单元上执行的代码可以在不再需要某些数据块的情况下向运行时指示，并且因此可以被驱逐和/或预取其他数据块。

6. 发明申请

WO2016060737A1 APPROXIMATION OF EXECUTION EVENTS USING MEMORY HIERARCHY MONITORING 审中-公开
标题翻译：使用记忆层次监测对执行事件的近似
公开(公告)号：WO2016060737A1
公开(公告)日：2016-04-21
申请号：PCT/US2015/046097
申请日：2015-08-20
申请人： QUALCOMM INCORPORATED
发明人： CHRISTODORESCU, Mihai , SALAJEGHEH, Mastooreh , SUAREZ GRACIA, Dario
IPC分类号： G06F11/34 , G06F11/30
CPC分类号： G06F3/0604 , G06F3/0653 , G06F3/0673 , G06F11/3003 , G06F11/3037 , G06F11/3471 , G06F21/56 , G06F2201/86 , G06F2201/865 , G06F2201/885 , G06F2221/034
摘要： Aspects include computing devices, systems, and methods for implementing monitoring communications between components and a memory hierarchy of a computing device. The computing device may determine at least one identifying factor for identifying execution of the processor-executable code. A communication between the components and the memory hierarchy of the computing device may be monitored for at least one communication factor of a same type as the at least one identifying factor. A determination whether a value of the at least one identifying factor matches a value of the at least one communication factor may be made. The computing device may determine that the processor-executable code is executed in response to determining that the value of the at least one identifying factor matches the value of the at least one communication factor.
摘要翻译：方面包括用于实现组件之间的监视通信和计算设备的存储器层次结构的计算设备，系统和方法。计算设备可以确定用于识别处理器可执行代码的执行的至少一个识别因素。可以针对与至少一个识别因素相同类型的至少一个通信因素来监视计算设备的组件和存储器层次之间的通信。可以进行至少一个识别因素的值是否与至少一个通信因素的值相匹配的确定。响应于确定至少一个识别因子的值与至少一个通信因子的值相匹配，计算设备可以确定执行处理器可执行代码。

7. 发明申请

WO2016122795A1 SYSTEM AND METHOD FOR ADAPTIVELY MANAGING REGISTERS WITH INOPERATIVE CELLS 审中-公开
标题翻译：用于适应性管理注射器与非营养细胞的系统和方法
公开(公告)号：WO2016122795A1
公开(公告)日：2016-08-04
申请号：PCT/US2015/066269
申请日：2015-12-17
申请人： QUALCOMM INCORPORATED
发明人： SUAREZ GRACIA, Dario , ROBATMILI, Behnam
IPC分类号： G06F9/30 , G06F1/32 , G06F11/00
CPC分类号： G06F9/30109 , G06F1/32 , G06F9/30105 , G06F9/30112 , G06F9/30141 , G06F9/3016 , G06F9/384 , G06F11/00
摘要： Systems and methods for adaptively managing registers in an instruction processor are disclosed. The system identifies one or more registers with inoperable cells. An operand manager identifies a set of operable cells within the one or more registers with inoperable cells and determines if a present instruction will use an operand that can be supported by the set of operable cells. When the set of operable cells can support the operand, the operand manager generates an assignment which is communicated to a register file manager.
摘要翻译：公开了一种用于自适应地管理指令处理器中的寄存器的系统和方法。系统识别一个或多个不可操作的单元的寄存器。操作数管理器使用不可操作的单元识别一个或多个寄存器内的一组可操作单元，并且确定当前指令是否将使用该组可操作单元支持的操作数。当可操作单元的组可以支持操作数时，操作数管理器产生一个传送给寄存器文件管理器的分配。

8. 发明申请

WO2015112763A1 HARDWARE ACCELERATION FOR INLINE CACHES IN DYNAMIC LANGUAGES 审中-公开
标题翻译：动态语言中的线性加速硬件加速
公开(公告)号：WO2015112763A1
公开(公告)日：2015-07-30
申请号：PCT/US2015/012529
申请日：2015-01-22
申请人： QUALCOMM INCORPORATED
发明人： ROBATMILI, Behnam , CASCAVAL, Gheorghe , KEDLAYA, Madhukar Nagaraja , SUAREZ GRACIA, Dario
IPC分类号： G06F9/44 , G06F12/08
CPC分类号： G06F9/4491 , G06F12/0802
摘要： Aspects include apparatuses, systems, and methods for hardware acceleration for inline caches in dynamic languages. An inline cache may be initialized for an instance of a dynamic software operation. A call of an initialized instance of the dynamic software operation may be executed by an inline cache hardware accelerator. The inline cache may be checked to determine that its data is current. When the data is current, the initialized instance of the dynamic software operation may be executed using the related inline cache data. When the data is not current, a new inline cache may be initialized for the instance of the dynamic software operation, including the not current data of a previously initialized instance of the dynamic software operation. The inline cache hardware accelerator may include an inline cache memory, a coprocessor, and/or a functional until one an inline cache pipeline connected to a processor pipeline.
摘要翻译：方面包括用于动态语言的内联高速缓存的硬件加速的装置，系统和方法。可以为动态软件操作的实例初始化内联缓存。动态软件操作的初始化实例的调用可以由内联高速缓存硬件加速器执行。可以检查内联高速缓存以确定其数据是当前的。当数据是最新的时，可以使用相关的在线高速缓存数据来执行动态软件操作的初始化实例。当数据不是当前的时候，可以为动态软件操作的实例初始化新的内联高速缓存，包括动态软件操作的先前初始化的实例的当前数据。内联高速缓存硬件加速器可以包括内联高速缓冲存储器，协处理器和/或功能，直到连接到处理器流水线的内联高速缓存流水线为止。

9. 发明申请

WO2015112762A1 HARDWARE ACCELERATION FOR INLINE CACHES IN DYNAMIC LANGUAGES 审中-公开
标题翻译：动态语言中的线性加速硬件加速
公开(公告)号：WO2015112762A1
公开(公告)日：2015-07-30
申请号：PCT/US2015/012527
申请日：2015-01-22
申请人： QUALCOMM INCORPORATED
发明人： ROBATMILI, Behnam , CASCAVAL, Gheorghe , KEDLAYA, Madhukar Nagaraja , SUAREZ GRACIA, Dario
IPC分类号： G06F9/44 , G06F12/08
CPC分类号： G06F12/0875 , G06F9/30145 , G06F9/3867 , G06F9/4491 , G06F12/0802 , G06F2212/452
摘要： Aspects include a computing devices, systems, and methods for hardware acceleration for inline caches in dynamic languages. An inline cache may be initialized for an instance of a dynamic software operation. A call of an initialized instance of the dynamic software operation may be executed by an inline cache hardware accelerator. The inline cache may be checked to determine that its data is current. When the data is current, the initialized instance of the dynamic software operation may be executed using the related inline cache data. When the data is not current, a new inline cache may be initialized for the instance of the dynamic software operation, including the not current data of a previously initialized instance of the dynamic software operation. The inline cache hardware accelerator may include an inline cache memory, a coprocessor, and/or a functional until one an inline cache pipeline connected to a processor pipeline.
摘要翻译：方面包括用于动态语言的内联高速缓存的硬件加速的计算设备，系统和方法。可以为动态软件操作的实例初始化内联缓存。动态软件操作的初始化实例的调用可以由内联高速缓存硬件加速器执行。可以检查内联高速缓存以确定其数据是当前的。当数据是最新的时，可以使用相关的在线高速缓存数据来执行动态软件操作的初始化实例。当数据不是当前的时候，可以为动态软件操作的实例初始化新的内联高速缓存，包括动态软件操作的先前初始化的实例的当前数据。内联高速缓存硬件加速器可以包括内联高速缓冲存储器，协处理器和/或功能，直到连接到处理器流水线的内联高速缓存流水线为止。

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