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1. 发明申请

WO2018013327A1 LOW-DROPOUT REGULATOR WITH BAND-REJECT POWER SUPPLY REJECTION RATIO FOR PHASE LOCKED LOOP VOLTAGE CONTROLLED OSCILLATOR 审中-公开
标题翻译：带禁止电源抑制比的低压差调节器用于锁相环电压控制振荡器
公开(公告)号：WO2018013327A1
公开(公告)日：2018-01-18
申请号：PCT/US2017/039276
申请日：2017-06-26
申请人： QUALCOMM INCORPORATED
发明人： SONG, Tongyu , HINRICHS, Jeffrey Mark
IPC分类号： H03L1/00 , G05F1/575 , H03L7/099
摘要： A voltage regulator includes a band limited reference voltage. The band limited reference voltage is generated from a supply voltage combined with a feedback path to provide a band reject power supply rejection ratio (PSRR). The voltage regulator also includes a feedforward path to extend the band reject PSRR.
摘要翻译：电压调节器包括带限参考电压。带限参考电压由与反馈路径结合的电源电压产生，以提供带阻电源抑制比（PSRR）。该电压调节器还包括一个前馈路径来扩展带阻PSRR。

2. 发明申请

WO2020023309A1 HIGH-SPEED LOW-POWER LEVEL-SHIFTING CLOCK BUFFER 审中-公开
公开(公告)号：WO2020023309A1
公开(公告)日：2020-01-30
申请号：PCT/US2019/042595
申请日：2019-07-19
申请人： QUALCOMM INCORPORATED
发明人： SONG, Tongyu
IPC分类号： H03K19/0185
摘要： A DC-coupled buffer is provided with two switch transistors controlled by a delayed version of an output signal for the DC-coupled buffer. A first one of the switch transistors functions to cut off a current discharged into ground that would otherwise flow while an input signal for the DC-coupled buffer is discharged. A remaining second one of the switch transistors functions to increase the operating speed of the DC-coupled buffer.

3. 发明申请

WO2016137768A1 TRANSMIT DIGITAL TO ANALOG CONVERTER (DAC) SPUR ATTENUATION 审中-公开
标题翻译：发送数字到模拟转换器（DAC）SPUR衰减
公开(公告)号：WO2016137768A1
公开(公告)日：2016-09-01
申请号：PCT/US2016/017815
申请日：2016-02-12
申请人： QUALCOMM INCORPORATED
发明人： SEO, Dongwon , YOU, Yang , JI, Honghao , SONG, Tongyu , SARIPALLI, Ganesh , MEHDIZAD TALEIE, Shahin
IPC分类号： G05F1/56 , G05F1/575
CPC分类号： H03M1/0604 , G05F1/56 , G05F1/575 , G05F3/18 , H02M3/156 , H03F3/24 , H03M1/00 , H03M1/70 , H03M1/747 , H04B1/0475 , H04B2001/0408
摘要： A method and apparatus for attenuating transmit digital to analog converter (DAC) spurs is provided. The method begins when a reference voltage is injected into an amplifier. Next, an output of the ground low drop-out regulator is measured and is them compared with the reference voltage. The output of the amplifier is then adjusted based on the results of the comparison. If the reference voltage is higher then the output of the ground low drop-out regulator the output of the amplifier is adjusted to ground. If the reference voltage is lower than the output of the ground low drop-out regulator then the output of the amplifier is adjusted to match the reference voltage.
摘要翻译：提供了用于衰减发射数模转换器（DAC）杂散的方法和装置。当将参考电压注入放大器时，该方法开始。接下来，测量接地低压降稳压器的输出，并将其与参考电压进行比较。然后根据比较结果调整放大器的输出。如果参考电压较高，则接地低压降稳压器的输出将放大器的输出调整到地。如果参考电压低于接地低压降稳压器的输出，则调节放大器的输出以匹配参考电压。

4. 发明申请

WO2014150838A1 TECHNIQUES TO REDUCE HARMONIC DISTORTIONS OF IMPEDANCE ATTENUATORS FOR LOW-POWER WIDEBAND HIGH-RESOLUTON DACS 审中-公开
标题翻译：降低低功耗宽带高分辨率DAC的阻抗衰减器谐波失真的技术
公开(公告)号：WO2014150838A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/024370
申请日：2014-03-12
申请人： QUALCOMM INCORPORATED
发明人： SONG, Tongyu , LEE, Sang Min , KONG, Derui , SEO, Dongwon
IPC分类号： H03M1/06 , H03F3/45 , H03M1/74
CPC分类号： H03M1/74 , H03F3/19 , H03F3/211 , H03F3/245 , H03F3/45192 , H03F3/4565 , H03F3/72 , H03F2203/45466 , H03F2203/45512 , H03F2203/45562 , H03F2203/45631 , H03F2203/45634 , H03F2203/45644 , H03F2203/45686 , H03F2203/45701 , H03F2203/45702 , H03F2203/7236 , H03M1/0614
摘要： A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.
摘要翻译：数模转换器（DAC）部分地包括响应于数字信号向一对当前求和节点提供电流的多个输入级，以及耦合在当前求和节点和输出端之间的阻抗衰减器的DAC。除了其他功能之外，阻抗衰减器还适用于增加输出负载的阻抗范围，以解决由于工艺，电压和温度的变化而导致的输出负载阻抗的变化，并且将由求和所看到的阻抗解耦节点从负载阻抗。阻抗衰减器还包括具有可编程共模增益带宽的差分输入差分输出放大器，以控制放大器的谐波失真。阻抗衰减器可选地包括一对交叉耦合电容器，以控制放大器的谐波失真。

5. 发明申请

WO2015167816A1 RESIDUAL ERROR SAMPLING AND CORRECTION CIRCUITS IN INL DAC CALIBRATIONS 审中-公开
标题翻译： INL DAC校准中的残留误差采样和校正电路
公开(公告)号：WO2015167816A1
公开(公告)日：2015-11-05
申请号：PCT/US2015/026237
申请日：2015-04-16
申请人： QUALCOMM INCORPORATED
发明人： SONG, Tongyu , KONG, Derui
IPC分类号： H03M1/10 , H03M1/74
CPC分类号： H03M1/1047 , H03M1/1057 , H03M1/68 , H03M1/742
摘要： In an aspect of the disclosure, a method and an apparatus are provided for calibrating a DAC. The apparatus calibrates a first DAC element, provides a residual current error resulting from the calibration, the residual current error being a difference between a calibrated current source of the first DAC element and a reference current source, stores the residual current error of the calibrated first DAC element in a first memory module using at least first and second storage elements coupled to a differential amplifier, and calibrates a second DAC element using the stored residual current error.
摘要翻译：在本公开的一方面，提供了一种用于校准DAC的方法和装置。该装置校准第一DAC元件，提供由校准导致的剩余电流误差，剩余电流误差是第一DAC元件的校准电流源与参考电流源之间的差，存储校准的第一个 DAC元件，其使用至少第一和第二存储元件耦合到差分放大器，并且使用所存储的剩余电流误差来校准第二DAC元件。

6. 发明申请

WO2014133767A1 CALIBRATION SYSTEMS AND METHODS FOR DIGITAL-TO-ANALOG CONVERTER 审中-公开
标题翻译：用于数字到模拟转换器的校准系统和方法
公开(公告)号：WO2014133767A1
公开(公告)日：2014-09-04
申请号：PCT/US2014/016170
申请日：2014-02-13
申请人： QUALCOMM INCORPORATED
发明人： SONG, Tongyu
IPC分类号： H03M1/10 , H03M1/74
CPC分类号： H03M1/1009 , H03M1/1061 , H03M1/742
摘要： Circuits, methods, non-transitory storage media can be configured to reduce calibration errors in a signal converter. A digital-to-analog converter can include a calibration circuit configured to calibrate a digital-to-analog converter (DAC) bit element using a residual error from a previously calibrated digital-to-analog converter (DAC) bit element. The residual error can be stored in memory.
摘要翻译：可以配置电路，方法，非暂时性存储介质以减少信号转换器中的校准误差。数模转换器可以包括被配置为使用来自先前校准的数模转换器（DAC）位元素的残差来校准数模转换器（DAC）位元件的校准电路。剩余错误可以存储在内存中。

7. 发明申请

WO2011041612A1 WIDEBAND DIGITAL TO ANALOG CONVERTER WITH BUILT-IN LOAD ATTENUATOR 审中-公开
标题翻译：宽带数字到模拟转换器与内置负载衰减器
公开(公告)号：WO2011041612A1
公开(公告)日：2011-04-07
申请号：PCT/US2010/051007
申请日：2010-09-30
申请人： QUALCOMM INCORPORATED , SEO, Dongwon , SARIPALLI, Ganesh , SONG, Tongyu , TALEIE, Shahin, Mehdizad , KONG, Derui
发明人： SEO, Dongwon , SARIPALLI, Ganesh , SONG, Tongyu , TALEIE, Shahin, Mehdizad , KONG, Derui
IPC分类号： H03M1/74
CPC分类号： H03M1/742 , H03F1/223 , H03F1/3241 , H03F3/195 , H03F3/245 , H03F3/45183
摘要： A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.
摘要翻译：描述用于数模转换的电路。该电路包括一个数模转换器（DAC）。 DAC包括双级联电流源和差分电流模式开关（DCMS）。电路还包括直流（DC）偏置级。该电路还包括负载衰减器。双级联电流源可以在DCMS和导轨电压之间。

8. 发明申请

WO2010115152A1 TECHNIQUES FOR NON-OVERLAPPING CLOCK GENERATION 审中-公开
标题翻译：非重叠时钟产生技术
公开(公告)号：WO2010115152A1
公开(公告)日：2010-10-07
申请号：PCT/US2010/029850
申请日：2010-04-02
申请人： QUALCOMM INCORPORATED , QUAN, Xiaohong , SONG, Tongyu , MATHE, Lennart , ALLADI, Dinesh, J.
发明人： QUAN, Xiaohong , SONG, Tongyu , MATHE, Lennart , ALLADI, Dinesh, J.
IPC分类号： H03L7/08 , H03K3/017 , H03M1/12
CPC分类号： H03L7/0812 , H03K5/1515 , H03K5/1565 , H03K2005/00039 , H03K2005/00097 , H03K2005/00286 , H03M1/12
摘要： Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non- overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non- overlapping time (tnlp) that is independent of manufacturing process variations.
摘要翻译：提供了用于在所需频率范围内产生精确的非重叠时间和时钟相位延迟时间的技术。在一种配置中，设备包括不重叠的时钟产生电路，其包括延迟锁定环（DLL）电路，该延迟锁定环路（DLL）电路又向与其耦合的时钟发生器电路产生控制电压。控制电压操作以保持由时钟发生器电路产生的非重叠延迟时钟信号的精确定时关系。在一个方面，DLL电路接收具有已知占空比的输入时钟，并且导出输出控制电压以将单位延迟固定到输入时钟周期的某一部分。在另一方面，时钟发生器电路包括耦合到DLL电路的多个电压控制延迟单元，以产生第一组时钟信号和从第一组时钟信号延迟的第二组时钟信号，重叠时间（tnlp），与制造过程变化无关。

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