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1. 发明申请

WO2023049589A1 MULTI-DIE INTEGRATED CIRCUIT PACKAGES FOR SUPPORTING HIGHER CONNECTION DENSITY, AND RELATED FABRICATION METHODS 审中-公开
公开(公告)号：WO2023049589A1
公开(公告)日：2023-03-30
申请号：PCT/US2022/075390
申请日：2022-08-24
申请人： QUALCOMM INCORPORATED
发明人： POPOVIC, Darko , LISK, Durodami , LI, Yue
IPC分类号： H01L25/10 , H01L23/00 , H01L23/538 , H01L25/00
摘要： Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods. The multi-die IC package includes split dies that provided in respective die packages that are stacked on top of each other to conserve package area. To support signal routing, including through-package signal routing that extends through the die package, each die package includes vertical interconnects disposed adjacent to their respective dies and coupled to a respective package substrate (and interposer substrate if provided) in the package substrate. In this manner, as an example, through-silicon-vias (TSVs) are not required to be fabricated in the multi-die IC package that extend through the dies themselves to provide signal routing between the respective die packages. In another example, space created between adjacent interposer substrates of stacked die packages, as stood off from each other through the interconnect bumps, provides an area for heat dissipation.

2. 发明申请

WO2023049578A1 SEMICONDUCTOR DIE WITH INTERCONNECT BUMP DESIGN EMPLOYING REPURPOSED SEED LAYER FOR FORMING ADDITIONAL SIGNAL PATHS TO BACK END-OF-LINE (BEOL) STRUCTURE, AND RELATED INTEGRATED CIRCUIT (IC) PACKAGE AND FABRICATION METHOD 审中-公开
公开(公告)号：WO2023049578A1
公开(公告)日：2023-03-30
申请号：PCT/US2022/075315
申请日：2022-08-23
申请人： QUALCOMM INCORPORATED
发明人： LI, Yue , LISK, Durodami , SUN, Jinying
IPC分类号： H01L23/485 , H01L21/60 , H01L25/065
摘要： A semiconductor die (302, 502, 702, 802, 1202, 1302) employs a repurposed seed layer (318, 518, 1218, 1318) for forming additional signal paths to a back end-of-line (BEOL) structure (310, 510, 1210, 1310) of the die (302, 502, 702, 802, 1202, 1302). A seed layer (318, 518, 1218, 1318) is disposed adjacent to the BEOL interconnect structure (310, 510, 1210, 1310) and selectively removed during fabrication to leave a portion of the seed layer (318, 518, 1218, 1318) repurposed that couples a UBM interconnect (326(4), 526(4)) that does not have an interconnect bump to a UBM interconnect (326(1), 326(2), 526(1), 1226, 1326) that has a raised interconnect bump (308, 508, 708, 710, 808, 1208, 1308), so that an additional routing path can be provided between the raised interconnect bump (308, 508, 708, 710, 808, 1208, 1308) and the BEOL interconnect structure (310, 510, 1210, 1310). A plurality of raised interconnect bumps (308(1), 308(2), 808) may be coupled together. The BEOL interconnect structure (310, 510, 1210, 1310) may comprise a metallization layer comprising a redistribution layer (RDL) (322, 522, 1224) with interconnects (320, 520) such as metal pads. The UBM interconnects (326, 526) may have an interconnect bump pitch (P2, P3), with the UBM interconnect (326(4), 526(4)) without an interconnect bump located a distance in a horizontal direction from the coupled raised interconnect bump (308(2), 508(1)) less than or greater than the interconnect bump pitch (P2, P3). The die (302, 502, 702) may further comprise a power distribution network (PDN), comprising a ground plane in the BEOL interconnect structure (310, 510) and a positive supply rail in the BEOL interconnect structure (310, 510), wherein the UBM interconnect (326(4), 526(4)) without an interconnect bump may be coupled to the ground plane of the power distribution network, to the positive supply rail of the power distribution network or to an input/output (I/O) signal node configured to carry an I/O signal. The semiconductor die (302, 502, 702, 802, 1202, 1302) may be included in an IC package (300, 500, 700, 800, 1200, 1300), the IC package (300, 500, 700, 800, 1200, 1300) comprising: a package substrate (304, 704, 804, 1204, 1304) and the die (302, 502, 702, 802, 1202, 1302) coupled to the package substrate (304, 704, 804, 1204, 1304) through the raised interconnect bump (308, 508, 708, 710, 808, 1208(1), 1308). The IC package (1200, 1300) may also comprise a second die (1202(2), 1302(2)), with a BEOL interconnect structure (1210(2)), UBM interconnects (1226(2), 1326(2)), a raised interconnect bump (1208(2), 1308(2)) and a seed layer (1218(2), 1318(2)) related to those of the first die (1202(1), 1302(1)), wherein the second die (1202(2)) may be stacked on the first die (1202(1)) or the two dies may be split dies (1302(1), 1302(2)) both coupled to the package substrate (1304) adjacent to each other in a horizontal direction and coupled to each other through the package substrate (1304) to provide a die-to-die (D2D) connection. In a method of fabricating the semiconductor die (302, 502, 702, 802, 1202, 1302), a photoresist layer (1102) may be formed and patterned on the seed layer (318), a metal material being then disposed in an opening (1104) in the photoresist layer (1102) to form the raised interconnect bump (308) and the photoresist layer (1102) being subsequently removed, wherein a second photoresist layer (1108) may be formed and patterned on the seed layer (318) and the raised interconnect bump (308), the seed layer (318) being then removed in a second opening (1110) of the second photoresist layer (1108) without removing the seed layer (318) coupling the UBM interconnects (326), followed by removing the second photoresist layer (1108).

3. 发明申请

WO2023091285A1 PACKAGE COMPRISING CHANNEL INTERCONNECTS LOCATED BETWEEN SOLDER INTERCONNECTS 审中-公开
公开(公告)号：WO2023091285A1
公开(公告)日：2023-05-25
申请号：PCT/US2022/048192
申请日：2022-10-28
申请人： QUALCOMM INCORPORATED
发明人： PATIL, Aniket , LISK, Durodami , WE, Hong Bok , PAYNTER, Charles David
IPC分类号： H01L23/538 , H01L25/10 , H05K1/14 , H01L25/065 , H01L25/18 , H01L23/00
摘要： A device comprising a first package and a second package coupled to the first package through a first plurality of solder interconnects. The first package includes a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.

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