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1. 发明申请

WO2019040238A1 EXPEDITING CACHE MISSES THROUGH CACHE HIT PREDICTION 审中-公开
公开(公告)号：WO2019040238A1
公开(公告)日：2019-02-28
申请号：PCT/US2018/044645
申请日：2018-07-31
申请人： QUALCOMM INCORPORATED
发明人： AL SHEIKH, Rami Mohammad , PRIYADARSHI, Shivam , DWIEL, Brandon , PALFRAMAN, David John , HOWER, Derek
IPC分类号： G06F12/084 , G06F12/0855 , G06F12/0897
CPC分类号： G06F12/0875 , G06F12/0811 , G06F12/084 , G06F12/0859 , G06F12/0897 , G06F2212/1016 , G06F2212/1024 , G06F2212/502 , G06F2212/507 , G06F2212/60 , G06F2212/62
摘要： A request to access data at a first physical address misses in a private cache of a processor. A confidence value is received for the first physical address based on a hash value of the first physical address. A determination is made that the received confidence value exceeds a threshold value. In response, a speculative read request specifying the first physical address is issued to a memory controller of a main memory to expedite a miss for the data at the first physical address in a shared cache.

2. 发明申请

WO2017030674A1 POWER EFFICIENT FETCH ADAPTATION 审中-公开
标题翻译：功率有效的FET适配
公开(公告)号：WO2017030674A1
公开(公告)日：2017-02-23
申请号：PCT/US2016/041696
申请日：2016-07-11
申请人： QUALCOMM INCORPORATED
发明人： PRIYADARSHI, Shivam , AL SHEIKH, Rami Mohammad , DAMODARAN, Raguram
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3802 , G06F9/3844 , G06F12/0875 , G06F2212/452
摘要： Systems and methods relate to an instruction fetch unit of a processor, such as a superscalar processor. The instruction fetch unit includes a fetch bandwidth predictor (FBWP) configured to predict a number of instructions to be fetched in a fetch group of instructions in a pipeline stage of the processor. A first entry of the FBWP corresponding to the fetch group corresponds to a prediction of the number of instructions to be fetched, based on occurrence and location of a predicted taken branch instruction in the fetch group and a confidence level associated with the predicted number in the prediction field. The instruction fetch unit is configured to fetch only the predicted number of instructions, rather than the maximum number of entries that can be fetched in the pipeline stage, if the confidence level is greater than a predetermined threshold. In this manner, wasteful fetching of instructions is avoided.
摘要翻译：系统和方法涉及诸如超标量处理器的处理器的指令提取单元。指令提取单元包括获取带宽预测器（FBWP），其被配置为预测将在处理器的流水线级中的取指令组中提取的指令数量。对应于取出组的FBWP的第一条目对应于基于取出组中预测的分支指令的出现和位置以及与所提取的预测数相关联的置信水平的待获取的指令数量的预测预测领域。如果置信水平大于预定阈值，则指令提取单元被配置为仅获取预测数量的指令，而不是在流水线级中可以获取的最大条目数。以这种方式，避免了浪费的指令提取。

3. 发明申请

WO2019040239A1 INTELLIGENT DATA PREFETCHING USING ADDRESS DELTA PREDICTION 审中-公开
公开(公告)号：WO2019040239A1
公开(公告)日：2019-02-28
申请号：PCT/US2018/044649
申请日：2018-07-31
申请人： QUALCOMM INCORPORATED
发明人： AL SHEIKH, Rami Mohammad , PRIYADARSHI, Shivam , DWIEL, Brandon , PALFRAMAN, David John , HOWER, Derek , CHOWDHURY, Muntaquim Faruk
IPC分类号： G06F9/355 , G06F9/38 , G06F9/345
CPC分类号： G06F12/0862 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F12/0875 , G06F12/1063 , G06F12/109 , G06F2212/452 , G06F2212/602
摘要： A first load instruction specifying a first virtual address misses in a data cache. A delta value is received based on a program counter value of the first load instruction. A second virtual address is computed based on the delta value and the first virtual address. Data associated with the second virtual address is then prefetched from a main memory to the data cache prior to a second load instruction specifying the second virtual address missing in the data cache.

4. 发明申请

WO2017151273A1 DYNAMIC PIPELINE THROTTLING USING CONFIDENCE-BASED WEIGHTING OF IN-FLIGHT BRANCH INSTRUCTIONS 审中-公开
标题翻译：动态管道使用基于置信度的飞行分支指令加权进行调节
公开(公告)号：WO2017151273A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/016704
申请日：2017-02-06
申请人： QUALCOMM INCORPORATED
发明人： PRIYADARSHI, Shivam , AL SHEIKH, Rami Mohammad , DAMODARAN, Raguram , MCILVAINE, Michael Scott , BRIDGES, Jeffrey Todd
IPC分类号： G06F9/38
摘要： Systems and methods for operating a processor include determining confidence levels, such as high, low, and medium confidence levels, associated with in-flight branch instructions in an instruction pipeline of the processor, based on counters used for predicting directions of the in-flight branch instructions. Numbers of in-flight branch instructions associated with each of confidence levels are determined. A weighted sum of the numbers weighted with weights corresponding to the confidence levels is calculated and the weighted sum is compared with a threshold. A throttling signal may be asserted to indicate that instructions are to be throttled in a pipeline stage of the instruction pipeline based on the comparison.
摘要翻译：用于操作处理器的系统和方法包括基于使用的计数器确定与处理器的指令流水线中的飞行中分支指令相关联的置信度水平，诸如高，低和中等置信度水平用于预测飞行中分支指令的方向。确定与每个置信度相关的飞行中分支指令的数量。计算用对应于置信水平的权重加权的数字的加权和，并将加权和与阈值进行比较。节制信号可以被断言以指示指令将在指令流水线的流水线阶段中基于比较而被节制。

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