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1. 发明申请

WO2008128097A3 PROGRAMMABLE GRAPHICS PROCESSING ELEMENT 审中-公开
标题翻译：可编程图形处理单元
公开(公告)号：WO2008128097A3
公开(公告)日：2008-12-24
申请号：PCT/US2008060103
申请日：2008-04-11
申请人： QUALCOMM INC , JIAO GUOFANG , CHEN LINGJUN FRANK , YU CHUN , DU YUN
发明人： JIAO GUOFANG , CHEN LINGJUN FRANK , YU CHUN , DU YUN
IPC分类号： G06F13/10 , G06T15/00 , G06T15/40 , G06T15/50
CPC分类号： G06T15/005 , G06T15/40 , G06T15/503
摘要： In general, this disclosure describes techniques for performing graphics operations using programmable processing units in a graphics processing unit (GPU). As described herein, a GPU includes a graphics pipeline that includes a programmable graphics processing element (PGPE). In accordance with the techniques described herein, an arbitrary set of instructions is loaded into the PGPE. Subsequently, the PGPE may execute the set of instructions in order to generate a new pixel object. A pixel object describes a displayable pixel. The new pixel object may represent a result of performing a graphics operation on a first pixel object. A display device may display a pixel described by the new pixel object.
摘要翻译：一般来说，本发明描述用于使用图形处理单元（GPU）中的可编程处理单元来执行图形操作的技术。如这里所描述的，GPU包括包含可编程图形处理元件（PGPE）的图形管线。根据这里描述的技术，任意指令集被加载到PGPE中。随后，PGPE可以执行该组指令以便生成新的像素对象。像素对象描述可显示的像素。新像素对象可以表示对第一像素对象执行图形操作的结果。显示设备可以显示由新像素对象描述的像素。

2. 发明申请

WO2010138870A3 GRAPHICS PROCESSING UNIT WITH DEFERRED VERTEX SHADING 审中-公开
标题翻译：图形处理单元，带有VERTEX SHADING
公开(公告)号：WO2010138870A3
公开(公告)日：2012-04-12
申请号：PCT/US2010036661
申请日：2010-05-28
申请人： QUALCOMM INC , JIAO GUOFANG , DU YUN , CHEN LINGJUN , YU CHUN
发明人： JIAO GUOFANG , DU YUN , CHEN LINGJUN , YU CHUN
IPC分类号： G06T15/00
CPC分类号： G06T15/40 , G06T1/20 , G06T15/005
摘要： Techniques are described for processing graphics images with a graphics processing unit (GPU) using deferred vertex shading. An example method includes the following: generating, within a processing pipeline of a graphics processing unit (GPU), vertex coordinates for vertices of each primitive within an image geometry, wherein the vertex coordinates comprise a location and a perspective parameter for each one of the vertices, and wherein the image geometry represents a graphics image; identifying, within the processing pipeline of the GPU, visible primitives within the image geometry based upon the vertex coordinates; and, responsive to identifying the visible primitives, generating, within the processing pipeline of the GPU, vertex attributes only for the vertices of the visible primitives in order to determine surface properties of the graphics image.
摘要翻译：描述了使用延迟顶点着色处理具有图形处理单元（GPU）的图形图像的技术。示例性方法包括以下：在图形处理单元（GPU）的处理流水线内生成图像几何中每个图元的顶点的顶点坐标，其中顶点坐标包括位置和透视参数顶点，并且其中图像几何表示图形图像; 在GPU的处理流水线内识别基于顶点坐标的图像几何图形内的可见原始图形; 并且响应于识别可见原语，在GPU的处理流水线内生成仅针对可见图元的顶点的顶点属性，以便确定图形图像的表面特性。

3. 发明申请

WO2007146574A3 CONVOLUTION FILTERING IN A GRAPHICS PROCESSOR 审中-公开
标题翻译：图形处理器中的变换滤波
公开(公告)号：WO2007146574A3
公开(公告)日：2009-08-27
申请号：PCT/US2007069663
申请日：2007-05-24
申请人： QUALCOMM INC , JIAO GUOFANG , DU YUN , YU CHUN , CHEN LINGJUN
发明人： JIAO GUOFANG , DU YUN , YU CHUN , CHEN LINGJUN
IPC分类号： G06F17/15 , G06T5/00 , G06T15/04
CPC分类号： G06F17/153 , G06T5/20 , G06T15/04
摘要： Techniques for performing convolution filtering using hardware normally available in a graphics processor are described. Convolution filtering of an arbitrary HxW grid of pixels is achieved by partitioning the grid into smaller sections, performing computation for each section, and combining the intermediate results for all sections to obtain a final result. In one design, a command to perform convolution filtering on a grid of pixels with a kernel of coefficients is received, e.g., from a graphics application. The grid is partitioned into multiple sections, where each section may be 2x2 or smaller. Multiple instructions are generated for the multiple sections, with each instruction performing convolution computation on at least one pixel in one section. Each instruction may include pixel position information and applicable kernel coefficients. Instructions to combine the intermediate results from the multiple instructions are also generated.
摘要翻译：描述使用图形处理器中通常可用的硬件执行卷积滤波的技术。通过将网格划分为更小的部分，对每个部分执行计算，并组合所有部分的中间结果以获得最终结果，实现了任意HxW像素网格的卷积滤波。在一种设计中，例如从图形应用程序接收用于对具有系数内核的像素网格进行卷积滤波的命令。网格被划分成多个部分，其中每个部分可以是2x2或更小。为多个部分生成多个指令，每个指令在一个部分中的至少一个像素上执行卷积计算。每个指令可以包括像素位置信息和可应用的内核系数。还会生成组合来自多条指令的中间结果的指令。

4. 发明申请

WO2008049110A3 PROGRAMMABLE BLENDING IN A GRAPHICS PROCESSING UNIT 审中-公开
标题翻译：图形处理单元中的可编程混合
公开(公告)号：WO2008049110A3
公开(公告)日：2008-07-17
申请号：PCT/US2007081952
申请日：2007-10-19
申请人： QUALCOMM INC , JIAO GUOFANG , YU CHUN , CHEN LINGJUN FRANK , DU YUN
发明人： JIAO GUOFANG , YU CHUN , CHEN LINGJUN FRANK , DU YUN
IPC分类号： G06T15/50
CPC分类号： G06T15/503 , G06T2210/32
摘要： Techniques for implementing blending equations for various blending modes with a base set of operations are described. Each blending equation may be decomposed into a sequence of operations. In one design, a device includes a processing unit that implements a set of operations for multiple blending modes and a storage unit that stores operands and results. The processing unit receives a sequence of instructions for a sequence of operations for a blending mode selected from the plurality of blending modes and executes each instruction in the sequence to perform blending in accordance with the selected blending mode. The processing unit may include (a) an ALU that performs at least one operation in the base set, e.g., a dot product, (b) a pre-formatting unit that performs gamma correction and alpha scaling of inbound color values, and (c) a post-formatting unit that performs gamma compression and alpha scaling of outbound color values.
摘要翻译：描述了用一组基本操作来实现各种混合模式的混合方程的技术。每个混合等式可以被分解为一系列操作。在一种设计中，设备包括处理单元，其执行用于多个混合模式的一组操作以及存储操作数和结果的存储单元。处理单元接收用于从多个混合模式中选择的混合模式的一系列操作的指令序列，并且执行该序列中的每个指令以根据所选择的混合模式执行混合。处理单元可以包括（a）在基本集合中执行至少一个操作的ALU，例如点积，（b）执行入站颜色值的伽马校正和阿尔法缩放的预格式化单元，以及（c））后格式化单元，用于执行出站颜色值的伽玛压缩和alpha缩放。

5. 发明申请

WO2008051989A2 3-D CLIPPING IN A GRAPHICS PROCESSING UNIT 审中-公开
标题翻译：图形处理单元中的三维裁剪
公开(公告)号：WO2008051989A2
公开(公告)日：2008-05-02
申请号：PCT/US2007082261
申请日：2007-10-23
申请人： QUALCOMM INC , JIAO GUOFANG , YU CHUN , CHEN LINGJUN FRANK , DU YUN
发明人： JIAO GUOFANG , YU CHUN , CHEN LINGJUN FRANK , DU YUN
IPC分类号： G06T15/00 , G06T15/30
CPC分类号： G06T1/20 , G06T11/40 , G06T11/60 , G06T15/005 , G06T15/30 , G06T19/00 , G09G5/393
摘要： A graphics processing unit (GPU) efficiently performs 3-dimensional (3-D) clipping using processing units used for other graphics functions. The GPU includes first and second hardware units and at least one buffer. The first hardware unit performs 3-D clipping of primitives using a first processing unit used for a first graphics function, e.g., an ALU used for triangle setup, depth gradient setup, etc. The first hardware unit may perform 3-D clipping by (a) computing clip codes for each vertex of each primitive, (b) determining whether to pass, discard or clip each primitive based on the clip codes for all vertices of the primitive, and (c) clipping each primitive to be clipped against clipping planes. The second hardware unit computes attribute component values for new vertices resulting from the 3-D clipping, e.g., using an ALU used for attribute gradient setup, attribute interpolation, etc. The buffer(s) store intermediate results of the 3-D clipping.
摘要翻译：图形处理单元（GPU）使用用于其他图形功能的处理单元有效地执行三维（3-D）裁剪。 GPU包括第一和第二硬件单元以及至少一个缓冲器。第一硬件单元使用用于第一图形功能的第一处理单元（例如，用于三角形设置，深度梯度设置等的ALU）来执行基元的3-D剪切。第一硬件单元可以通过（ a）计算每个图元的每个顶点的剪辑代码，（b）基于图元的所有顶点的剪辑代码，确定是否通过，丢弃或剪切每个图元，以及（c）剪裁每个图元以剪切平面。第二硬件单元例如使用用于属性梯度设置，属性内插等的ALU来计算由3-D裁剪产生的新顶点的属性分量值。缓冲器存储3-D裁剪的中间结果。

6. 发明申请

WO2009018385A3 SCHEME FOR PACKING AND LINKING OF VARIABLES IN GRAPHICS SYSTEMS 审中-公开
标题翻译：在图形系统中包含和链接变量的方案
公开(公告)号：WO2009018385A3
公开(公告)日：2009-03-26
申请号：PCT/US2008071655
申请日：2008-07-30
申请人： QUALCOMM INC , JIAO GUOFANG , BOURD ALEXEI V , YU CHUN , CHEN LINGJUN , DU YUN
发明人： JIAO GUOFANG , BOURD ALEXEI V , YU CHUN , CHEN LINGJUN , DU YUN
IPC分类号： G06T1/60
CPC分类号： G06T1/60 , G06T15/005
摘要： A wireless device which performs a first-level compiler packing process and a second-level hardware packing process on varyings. The compiler packing process packs two or more shader variables (varyings or attributes) whose sum of components equals M into a shared M-dimensional (MD) vector register. The hardware packing consecutively packs M components of the shader variables (varyings or attributes) and any remaining variables into a vertex cache or other storage medium.
摘要翻译：执行第一级编译器打包处理的无线设备和关于变化的二级硬件打包过程。编译器打包过程将两个或更多个成分等于M的着色器变量（变化或属性）打包成共享的M维（MD）向量寄存器。硬件包装将着色器变量（变化或属性）的M个组件以及任何剩余变量包含在顶点缓存或其他存储介质中。

7. 发明申请

WO2008048940A2 GRAPHICS PROCESSING UNIT WITH SHARED ARITHMETIC LOGIC UNIT 审中-公开
标题翻译：具有共享算术逻辑单元的图形处理单元
公开(公告)号：WO2008048940A2
公开(公告)日：2008-04-24
申请号：PCT/US2007081428
申请日：2007-10-15
申请人： QUALCOMM INC , JIAO GUOFANG , RUTTENBERG BRAIN , YU CHUN , DU YUN
发明人： JIAO GUOFANG , RUTTENBERG BRAIN , YU CHUN , DU YUN
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.
摘要翻译：本公开描述了使用一个或多个共享算术逻辑单元（ALU）的图形处理单元（GPU）流水线。为了促进ALU的这种共享，所公开的GPU流水线的阶段可以相对于传统的GPU管线重新排列。此外，通过重新排列GPU流水线的各个阶段，可以在图像处理中实现效率。与传统GPU流水线不同，例如，属性梯度建立阶段可以在流水线后面定位，并且属性内插器阶段可以立即跟随属性梯度建立阶段。这允许通过属性渐变设置和属性内插器阶段共享ALU。还描述了用于GPU流水线的若干其它技术和特征，其可以提高性能并且可能实现额外的处理效率。

8. 发明申请

WO2008101210A3 EFFICIENT 2-D AND 3-D GRAPHICS PROCESSING 审中-公开
标题翻译：有效的二维和三维图形处理
公开(公告)号：WO2008101210A3
公开(公告)日：2009-10-22
申请号：PCT/US2008054162
申请日：2008-02-15
申请人： QUALCOMM INC , JIAO GUOFANG , DORBIE ANGUS M , YUN JAY C , DU YUN , YU CHUN
发明人： JIAO GUOFANG , DORBIE ANGUS M , YUN JAY C , DU YUN , YU CHUN
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06T11/40 , G09G5/363
摘要： Techniques for supporting both 2-D and 3-D graphics are described. A graphics processing unit (GPU) may perform 3-D graphics processing in accordance with a 3-D graphics pipeline to render 3-D images and may also perform 2-D graphics processing in accordance with a 2-D graphics pipeline to render 2-D images. Each stage of the 2-D graphics pipeline may be mapped to at least one stage of the 3-D graphics pipeline. For example, a clipping, masking and scissoring stage in 2-D graphics may be mapped to a depth test stage in 3-D graphics. Coverage values for pixels within paths in 2-D graphics may be determined using rasterization and depth test stages in 3-D graphics. A paint generation stage and an image interpolation stage in 2-D graphics may be mapped to a fragment shader stage in 3-D graphics. A blending stage in 2-D graphics may be mapped to a blending stage in 3-D graphics.
摘要翻译：描述了支持2-D和3-D图形的技术。图形处理单元（GPU）可以根据3-D图形流水线执行3D图形处理以渲染3-D图像，并且还可以根据2-D图形流水线执行2-D图形处理以呈现2 -D图像。 2-D图形管线的每个阶段可以映射到3-D图形流水线的至少一个阶段。例如，2-D图形中的裁剪，掩蔽和裁剪阶段可能被映射到3-D图形中的深度测试阶段。 2-D图形中路径内像素的覆盖值可以使用3-D图形中的光栅化和深度测试阶段来确定。 2-D图形中的油漆生成阶段和图像插值阶段可以映射到3-D图形中的片段着色器阶段。 2-D图形中的混合阶段可以映射到3-D图形的混合阶段。

9. 发明申请

WO2009036314A3 FRAGMENT SHADER BYPASS IN A GRAPHICS PROCESSING UNIT, AND APPARATUS AND METHOD THEREOF 审中-公开
标题翻译：图形处理单元中的片状阴影旁边，及其装置及方法
公开(公告)号：WO2009036314A3
公开(公告)日：2009-07-09
申请号：PCT/US2008076227
申请日：2008-09-12
申请人： QUALCOMM INC , JIAO GUOFANG , DU YUN , YU CHUN
发明人： JIAO GUOFANG , DU YUN , YU CHUN
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： Configuration information is used to make a determination to bypass fragment shading by a shader unit of a graphics processing unit, the shader unit capable of performing both vertex shading and fragment shader. Based on the determination, the shader unit performs vertex shading and bypasses fragment shading. A processing element other than the shader unit, such as a pixel blender, can be used to perform some fragment shading. Power is managed to 'turn off' power to unused components in a case that fragment shading is bypassed. For example, power can be turned off to a number of arithmetic logic units, the shader unit using the reduced number of arithmetic logic unit to perform vertex shading. At least one register bank of the shader unit can be used as a FIFO buffer storing pixel attribute data for use, with texture data, to fragment shading operations by another processing element.
摘要翻译：配置信息用于确定通过图形处理单元的着色器单元绕过片段着色，着色器单元能够执行顶点着色和片段着色。基于确定，着色器单元执行顶点着色并绕过片段着色。可以使用除着色器单元之外的处理元件，例如像素混合器，以执行某些片段着色。在绕过片段着色的情况下，功率被设计为“关闭”未使用组件的电源。例如，功率可以关闭到多个算术逻辑单元，着色器单元使用减少数量的算术逻辑单元来执行顶点着色。着色器单元的至少一个寄存器组可以用作FIFO缓冲器，其存储与纹理数据一起使用的像素属性数据，以分割另一个处理元件的着色操作。

10. 发明申请

WO2009049255A2 DEMAND-BASED POWER CONTROL IN A GRAPHICS PROCESSING UNIT 审中-公开
标题翻译：图形处理单元中基于需求的功率控制
公开(公告)号：WO2009049255A2
公开(公告)日：2009-04-16
申请号：PCT/US2008079644
申请日：2008-10-10
申请人： QUALCOMM INC , DU YUN , YU CHUN , JIAO GUOFANG
发明人： DU YUN , YU CHUN , JIAO GUOFANG
IPC分类号： G06F1/32 , G06F9/38
CPC分类号： G06F1/3203 , G06F1/3287 , G06T1/20 , Y02D10/171 , Y02D50/20
摘要： Disclosed herein is power controller for use with a graphics processing unit. The power controller monitors, manages and controls power supplied to components of a pipeline of the graphics processing unit. The power controller determining whether and to what extent power is to be supplied to a pipeline component based on status information received by the power controller in connection with the pipeline component. The power controller is capable of identifying a trend using the received status information, and determining whether and to what extent power is to be supplied to a pipeline component based on the identified trend.
摘要翻译：这里公开了与图形处理单元一起使用的功率控制器。功率控制器监视，管理和控制提供给图形处理单元的管线的组件的电力。功率控制器基于由电力控制器与流水线部件相关联的状态信息来确定是否以及在何种程度上向管道部件提供功率。功率控制器能够使用接收到的状态信息来识别趋势，并且基于所识别的趋势来确定是否以及在何种程度上向管道部件供电。

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