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1. 发明申请

WO2015153645A1 MEMORY MIGRATION IN PRESENCE OF LIVE MEMORY TRAFFIC 审中-公开
标题翻译：存在内存流量存在的内存迁移
公开(公告)号：WO2015153645A1
公开(公告)日：2015-10-08
申请号：PCT/US2015/023641
申请日：2015-03-31
申请人： ORACLE INTERNATIONAL CORPORATION
发明人： VAHIDSAFA, Ali , CHEUNG, Connie, Wai Mun
IPC分类号： G06F12/06 , G06F3/06 , G06F11/20
CPC分类号： G06F11/2094 , G06F3/0647 , G06F11/141 , G06F11/20 , G06F11/2069 , G06F12/0646 , G06F12/1036 , G06F2212/656
摘要： A method for memory migration between addressing schemes, including: receiving a first request to access a first memory address and a second request to access a second memory address; comparing the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un- migrated addresses; tagging the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending the first request to a first memory controller unit (MCU) and the second request to a second MCU.
摘要翻译：一种用于寻址方案之间的存储器迁移的方法，包括：接收访问第一存储器地址的第一请求和访问第二存储器地址的第二请求; 将第一存储器地址和第二存储器地址与引用屏障地址的屏障指针进行比较，并分离迁移的地址和未迁移的地址; 响应于所述第一存储器地址位于所述屏障地址的未迁移侧，用指示所述第一寻址方案的第一标签来标记所述第一请求; 响应于所述第二存储器地址位于所述屏障地址的迁移侧，用指示所述第二寻址方案的第二标签来标记所述第二请求; 并将第一请求发送到第一存储器控制器单元（MCU），并将第二请求发送给第二MCU。

2. 发明申请

WO2014121057A1 ROTATIONAL SYNCHRONIZER CIRCUIT FOR METASTABLITY RESOLUTION 审中-公开
标题翻译：旋转同步电路电路解决方案
公开(公告)号：WO2014121057A1
公开(公告)日：2014-08-07
申请号：PCT/US2014/014114
申请日：2014-01-31
申请人： ORACLE INTERNATIONAL CORPORATION
发明人： MASLEID, Robert, P. , VAHIDSAFA, Ali
IPC分类号： H04L7/02 , H04L25/05
CPC分类号： H03L7/00 , H04L7/005 , H04L7/02 , H04L25/05
摘要： A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input.
摘要翻译：公开了一种用于亚稳定性分辨率的旋转同步器。同步器包括多个M + 1个锁存器，每个锁存器被耦合以通过公共数据输入来接收数据。所述同步器还包括多路复用器，其具有N个输入端，每个输入端分别被耦合以从所述M + 1锁存器中对应的一个锁存器的输出端接收数据，以及输出端，其中，所述多路复用器被配置为选择其输入之一耦合到所述输出端。控制电路被配置为使得多路复用器响应于N个连续时钟脉冲顺序地选择M + 1个锁存器的输出，并且还被配置为使得M + 1锁存器顺序地锁存通过公共数据输入接收到的数据。

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