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1. 发明申请

WO2010106484A1 BOND FRAME INTEGRATED IN ELECTRONIC CIRCUIT 审中-公开
标题翻译：绑定在电子电路中的框架
公开(公告)号：WO2010106484A1
公开(公告)日：2010-09-23
申请号：PCT/IB2010/051111
申请日：2010-03-15
申请人： NXP B.V. , REIMANN, Klaus , LIU, Zidong , STEENEKEN, Peter,Gerard , WUNNICKE, Olaf , ROEST, Aarnoud, Laurens
发明人： REIMANN, Klaus , LIU, Zidong , STEENEKEN, Peter,Gerard , WUNNICKE, Olaf , ROEST, Aarnoud, Laurens
IPC分类号： H01L23/10 , B81B7/00 , H01L23/64 , H01L23/66
CPC分类号： H01L23/645 , B81B7/0077 , B81B7/02 , H01L23/10 , H01L23/66 , H01L2223/6677 , H01L2924/0002 , H01L2924/01079 , H01L2924/09701 , H01L2924/3011 , H01L2924/00
摘要： The invention relates to encapsulated integrated RF circuits comprising an integrated bond frame. Many integrated circuits need packaged for protection of the circuit or to connect the fine pitch of IC pins to the coarse pitch of a printed circuit board. It is known that passive components such as coils can be integrated into, e.g., lead-frame packages. Most MEMS (Micro Electro Mechanical Systems) require special packages, i.e., hermetic packages. Prominent examples are capacitive or galvanic MEMS switches for RF. A small and cost-effective package will lead to a wafer-scale package, where the MEMS wafer itself forms one part of the package. The other half can be another wafer that is bonded on the MEMS wafer, e.g., by eutectic bonding. The closed bond frame between the wafers forms an electrically coupled inductive element.
摘要翻译：本发明涉及包括集成结合框架的封装的集成RF电路。许多集成电路需要封装以保护电路或将IC引脚的精细间距连接到印刷电路板的粗略间距。已知诸如线圈的无源部件可以集成到例如引线框架封装中。大多数MEMS（微机电系统）需要特殊的封装，即密封封装。突出的例子是RF的电容或电流MEMS开关。一个小而具有成本效益的封装将导致晶片级封装，其中MEMS晶片本身构成封装的一部分。另一半可以是例如通过共晶接合结合在MEMS晶片上的另一个晶片。晶片之间的闭合键合框架形成电耦合的电感元件。

2. 发明申请

WO2010049864A2 GENERATING AND EXPLOITING AN ASYMMETRIC CAPACITANCE HYSTERESIS OF FERROELECTRIC MIM CAPACITORS 审中-公开
标题翻译：发生和开发铁电MIM电容器的非对称电容滞后
公开(公告)号：WO2010049864A2
公开(公告)日：2010-05-06
申请号：PCT/IB2009/054704
申请日：2009-10-24
申请人： NXP B.V. , ROEST, Aarnoud, Laurens , KLEE, Mareike , MAUCZOK, Rudiger, Gunter , REIMANN, Klaus , JOEHREN, Michael
发明人： ROEST, Aarnoud, Laurens , KLEE, Mareike , MAUCZOK, Rudiger, Gunter , REIMANN, Klaus , JOEHREN, Michael
IPC分类号： H01L27/02 , G11C11/56 , H01L27/115
CPC分类号： H01L27/0251 , G11C11/22 , G11C11/221 , H01L27/11502 , H01L28/55
摘要： The present invention relates to an electric component comprising at least one first MIM capacitor having a ferroelectric insulator with a dielectric constant of at least 100 between a first capacitor electrode of a first electrode material and a second capacitor electrode of a second electrode material. The first and second electrode materials are selected such that the first MIM capacitor exhibits, as a function of a DC voltage applicable between the first and second electrodes, an asymmetric capacitance hysteresis that lets the first MIM capacitor, in absence of the DC voltage, assume one of at least two possible distinct capacitance values, in dependence on a polarity of a switching voltage last applied to the capacitor, the switching voltage having an amount larger than a threshold-voltage amount. The invention is applicable for ESD sensors, memories and high-frequency devices.
摘要翻译：本发明涉及包括至少一个第一MIM电容器的电子元件，该电容器具有在第一电极材料的第一电容器电极和第二电容器电极之间具有至少100的介电常数的铁电绝缘体的第二电极材料。第一和第二电极材料被选择为使得第一MIM电容器根据可应用于第一和第二电极之间的DC电压呈现不对称电容滞后，其使得第一MIM电容器在没有DC电压的情况下假定依赖于最后施加到电容器的开关电压的极性，至少两个可能不同的电容值中的一个，开关电压具有大于阈值电压量的量。本发明适用于ESD传感器，存储器和高频器件。

3. 发明申请

WO2010103474A1 MEMS ELECTROSTATIC ACTUATOR 审中-公开
标题翻译： MEMS静电执行器
公开(公告)号：WO2010103474A1
公开(公告)日：2010-09-16
申请号：PCT/IB2010/051036
申请日：2010-03-10
申请人： NXP B.V. , REIMANN, Klaus , ROEST, Aarnoud, Laurens , LIU, Jin
发明人： REIMANN, Klaus , ROEST, Aarnoud, Laurens , LIU, Jin
IPC分类号： B81B3/00 , H01G5/16 , H01H1/00 , H01G5/011
CPC分类号： H01G5/0136 , H01G5/011 , H01G5/16
摘要： A MEMS electrostatic actuator comprises first and second opposing electrode arrangements, wherein at least one of the electrode arrangements is movable. A dielectric material (24) is adjacent the one of the electrode arrangements (22). The second electrode arrangement is patterned such that it includes electrode areas (26) and spaces adjacent the electrode areas, wherein the dielectric material (24) extends at least partially in or over the spaces. The invention uses a multitude of electrode portions as one plate. The electric field lines thus form clusters between the individual electrode portions and the opposing electrode. This arrangement provides an extended range of continuous actuation and tunability.
摘要翻译： MEMS静电致动器包括第一和第二相对电极装置，其中电极装置中的至少一个是可移动的。电介质材料（24）与电极装置（22）中的一个相邻。第二电极布置被图案化，使得其包括电极区域（26）和邻近电极区域的空间，其中电介质材料（24）至少部分地延伸到空间中或上方。本发明使用多个电极部分作为一个板。因此，电场线在单个电极部分和相对电极之间形成簇。这种布置提供了连续致动和可调性的扩展范围。

4. 发明申请

WO2010076733A1 PHYSICAL STRUCTURE FOR USE IN A PHYSICAL UNCLONABLE FUNCTION 审中-公开
标题翻译：物理结构在物理上的不可分割的功能
公开(公告)号：WO2010076733A1
公开(公告)日：2010-07-08
申请号：PCT/IB2009/055887
申请日：2009-12-21
申请人： NXP B.V. , ROEST, Aarnoud, Laurens , VAN LEUKEN-PETERS, Linda , WOLTERS, Robertus, Adrianus, Maria
发明人： ROEST, Aarnoud, Laurens , VAN LEUKEN-PETERS, Linda , WOLTERS, Robertus, Adrianus, Maria
IPC分类号： H01L23/58
CPC分类号： H01L23/576 , G06F21/73 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device comprising a physical structure (50) for use in a physical unclonable function, wherein the physical structure (50) comprises a lead-zirconium titanate layer (25), and a silicon-comprising dielectric layer (27) deposited on the lead-zirconium-titanate layer (25), wherein the silicon-comprising dielectric layer (27) has a rough surface (SR), the physical structure (50) further comprising a conductive layer (30) provided on the rough surface (SR) of the silicon-comprising dielectric layer (27). The invention further relates to a method of manufacturing such semiconductor device. The invention also relates to a card, such as a smartcard, and to a RFID tag comprising such semiconductor device. The inventors have found that depositing of a silicon- comprising dielectric layer (27) on a lead-zirconium titanate layer (25) using vapor deposition results in a silicon-comprising dielectric layer (27) having a rough surface (SR). This rough surface (SR) can be used in a PUF to make a resistor (R) with a variable random value by depositing a conductive layer (30) on the rough surface (SR). Alternatively, the combination of both layers (25, 27) can be used in a PUF as composite dielectric to make a capacitor (C) with a variable random capacitance value.
摘要翻译：本发明涉及一种半导体器件，其包括用于物理不可克隆功能的物理结构（50），其中所述物理结构（50）包括钛酸铅锆层（25）和含硅介电层（27）沉积在铅钛酸锆层（25）上，其中含硅介电层（27）具有粗糙表面（SR），物理结构（50）还包括设置在粗糙表面上的导电层（30）（27）的硅（SR）。本发明还涉及制造这种半导体器件的方法。本发明还涉及诸如智能卡的卡，以及包括这种半导体器件的RFID标签。本发明人已经发现，使用气相沉积在含钛的钛酸铅层（25）上沉积含硅的介电层（27）导致具有粗糙表面（SR）的含硅介电层（27）。通过在粗糙表面（SR）上沉积导电层（30），该粗糙表面（SR）可用于PUF中以制造具有可变随机值的电阻器（R）。或者，两层（25,27）的组合可以用作PUF作为复合电介质，以制造具有可变随机电容值的电容器（C）。

5. 发明申请

WO2010049859A1 3D INTEGRATION OF A MIM CAPACITOR AND A RESISTOR 审中-公开
标题翻译： MIM电容器和电阻器的3D集成
公开(公告)号：WO2010049859A1
公开(公告)日：2010-05-06
申请号：PCT/IB2009/054678
申请日：2009-10-22
申请人： NXP B.V. , ROEST, Aarnoud, Laurens , KLEE, Mareike , MAUCZOK, Rudiger, Gunter , VAN LEUKEN-PETERS, Linda , WOLTERS, Robertus, Adrianus, Maria
发明人： ROEST, Aarnoud, Laurens , KLEE, Mareike , MAUCZOK, Rudiger, Gunter , VAN LEUKEN-PETERS, Linda , WOLTERS, Robertus, Adrianus, Maria
IPC分类号： H01L21/02 , H01L23/522 , H01L27/02 , H01L27/06
CPC分类号： H01L28/55 , H01L23/5223 , H01L23/5228 , H01L27/0688 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.
摘要翻译：电子部件技术领域本发明涉及一种电子部件，其在基板上包括至少一个集成MIM电容器，（114）部分地或完全覆盖顶部电容器电极（118）并被制成的电绝缘的第一覆盖层（120）的含铅介电材料，以及在第一覆盖层上的顶部阻挡层（122）。顶部阻挡层用于避免在第一覆盖层暴露于还原物质时第一覆盖层所包含的引线原子的还原。在顶部阻挡层上的电绝缘的第二覆盖层（124）的介电常数比第一覆盖层的介电常数小，从而形成覆盖层结构的低寄生电容。所描述的具有中间顶部阻挡层的覆盖层结构允许在顶部制造高精度电阻层（126.1）。

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