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    • 1. 发明申请
    • METHOD AND SYSTEM FOR BLOCK CIPHER ENCRYPTION
    • 用于块密码加密的方法和系统
    • WO2008117142A9
    • 2008-10-02
    • PCT/IB2007/054592
    • 2007-11-12
    • NDS LIMITEDMANTIN, ItsikWAISBARD, ErezKIPNIS, Aviad
    • MANTIN, ItsikWAISBARD, ErezKIPNIS, Aviad
    • H04L9/06
    • A method and system of encrypting a block of data is described, the method including providing a combining unit operative to combine a key with a block of data, the block of data expressed as a block of bits, providing a mix and condense unit (MAC) operative to mix bits included in the block of bits among themselves, providing a plurality of layers of S-boxes, the S-boxes operative to receive an input including an input which has not yet been input into the mix and condense unit and to provide an output including an input to the mix and condense unit, receiving an input including the block of data expressed as the block of bits, combining, at the combining unit, the block of bits with a key, receiving an output of the combining unit as an input, substituting bits including the input to the plurality of layers of S-boxes with bits including the output of the plurality of layers of S-boxes, outputting the output of the plurality of layers of S-boxes to the mix and condense unit, and mixing, at the mix and condense unit, the output of the plurality of layers of S-boxes, thereby producing an encrypted block of bits.
    • 描述了一种对数据块进行加密的方法和系统,该方法包括提供组合单元,该组合单元用于将密钥与数据块进行组合,该数据块表示为位块, 提供混合和压缩单元(MAC),其操作以混合包括在它们之间的比特块中的比特,提供多个S盒层,这些S盒操作用于接收包括尚未输入的输入的输入 进入混合和压缩单元,并提供包括输入到混合和压缩单元的输出,接收包括表示为比特块的数据块的输入,在组合单元处将比特块与键合并 ,接收所述组合单元的输出作为输入,用包括所述多个S盒层的所述输出的位替换包括所述输入的位到所述多个S盒的层,输出所述多个S盒的所述输出 S盒到混合和凝聚 单元,并且在混合和压缩单元处混合多个S盒的输出,由此产生加密的比特块。
    • 6. 发明申请
    • IMPROVED CIPHER SYSTEM
    • 改进的CIPHER系统
    • WO2006111950A2
    • 2006-10-26
    • PCT/IL2006/000312
    • 2006-03-09
    • NDS LIMITEDMANTIN, ItsikSELLA, YaronWAISBARD, Erez
    • MANTIN, ItsikSELLA, YaronWAISBARD, Erez
    • G06F21/24
    • G06F21/74G06F21/72G06F2221/2105H04L9/0662
    • A system including a pseudo-random number generator having a register to store an extended state having a reduced state and a dynamic constant, an initialization module to initialize a part of the extended state based on a Key and/or an Initial Value, a state update module to update the reduced state, an output word module to generate output words, the state update module and the output word module being adapted to operate through cyclical rounds, each round including updating the reduced state and then generating one of the output words, and an update dynamic constant module to update the dynamic constant, wherein in a majority of the rounds, updating of the reduced state and/or generation of the output word is based on the dynamic constant, and the dynamic constant is only updated in a minority of the rounds. Related apparatus and method are also described.
    • 一种包括具有存储具有缩减状态和动态常数的扩展状态的寄存器的伪随机数发生器的系统,用于基于Key初始化部分扩展状态的初始化模块和/或初始值,状态 更新模块来更新缩减状态,输出字模块生成输出字,所述状态更新模块和所述输出字模块适于通过周期性循环进行操作,每轮包括更新所述简化状态,然后生成所述输出字之一, 以及更新动态常数模块来更新动态常数,其中在大部分回合中,减小状态的更新和/或输出字的生成基于动态常数,并且动态常数仅在少数情况下更新 的回合。 还描述了相关装置和方法。
    • 7. 发明申请
    • SECRETS RENEWABILITY
    • 秘密可再生能力
    • WO2014106781A1
    • 2014-07-10
    • PCT/IB2013/055658
    • 2013-07-10
    • NDS LIMITEDKARA-IVANOV, MichaelKIPNIS, AviadREINMAN, TzachyMANGELL, EfraimWAISBARD, ErezBELENKY, Yaacov
    • KARA-IVANOV, MichaelKIPNIS, AviadREINMAN, TzachyMANGELL, EfraimWAISBARD, ErezBELENKY, Yaacov
    • H04L9/08
    • H04L9/0861H04L9/0869
    • A method, system and apparatus for deriving a secondary secret from a root secret are described, the method, system and apparatus including reserving a memory buffer included in an integrated circuit, the memory buffer being large enough to contain all of the bits which will include the secondary secret, receiving a plurality of bits from a root secret, the root secret being stored in a secure memory of the integrated circuit, inputting the plurality of bits from the root secret and at least one control bit into a permutation network, and thereby producing a multiplicity of output bits, the at least one control bit including one of one bit of a value g, and one bit an output of a function which receives g as an input, receiving the multiplicity of output bits from the permutation network, inputting the multiplicity of output bits from the permutation network into a plurality of logic gates, thereby combining the multiplicity of output bits, wherein a fixed number of bits is output from the logic gates, inputting the fixed number of bits output by the logic gates into an error correcting code module, the fixed number of bits output by the logic gates including a first group of intermediate output bits and a second group of intermediate output bits and receiving output bits from the error correcting code module, the output bits of the error correcting code module including the first group of intermediate output bits as changed by the error correcting code module, where the change depends on the second group of intermediate output bits, filling non-filled registers in the reserved memory buffer with the first group of intermediate output bits as changed by the error correcting code module, and repeating the steps of "receiving a plurality of bits from a root secret" through "filling non-filled registers in the reserved memory buffer" until the entire secondary secret is derived, wherein the steps of "receiving a plurality of bits from a root secret" through "filling non-filled registers in the reserved memory buffer" are performed in a single clock cycle of the integrated circuit. Related apparatus, methods and systems are also described.
    • 描述了用于从根秘密导出第二秘密的方法,系统和装置,所述方法,系统和装置包括保留包括在集成电路中的存储器缓冲器,所述存储器缓冲器足够大以包含将包括的所有位 第二秘密,从根秘密接收多个比特,根秘密被存储在集成电路的安全存储器中,从根秘密输入多个比特和至少一个控制比特进入置换网络,从而 产生多个输出比特,所述至少一个控制比特包括值g的一个比特中的一个,一个比特作为接收g作为输入的函数的输出,从置换网络接收多个输出比特,输入 从置换网络到多个逻辑门的多个输出比特,从而组合多个输出比特,其中固定比特数从 逻辑门,将由逻辑门输出的固定位数输入到纠错码模块中,逻辑门输出的固定位数包括第一组中间输出位和第二组中间输出位,并接收 来自纠错码模块的输出位,纠错码模块的输出位包括由纠错码模块改变的第一组中间输出位,其中改变取决于第二组中间输出位, 所述预留存储器缓冲器中的所述第一组中间输出位的补充寄存器被所述纠错码模块改变,并且重复“从根秘密接收多个位”的步骤,通过“将未填充寄存器 保留的存储器缓冲器“,直到导出完整的二级秘密,其中”通过“不填入”从“根秘密接收多个比特” 在保留的存储器缓冲器中的n个填充寄存器“在集成电路的单个时钟周期中执行。 还描述了相关装置,方法和系统。
    • 8. 发明申请
    • TIME INFORMATION MANAGEMENT SYSTEM
    • 时间信息管理系统
    • WO2007148319A2
    • 2007-12-27
    • PCT/IL2007/000561
    • 2007-05-09
    • NDS LIMITEDWAISBARD, ErezSOLOW, Hillel
    • WAISBARD, ErezSOLOW, Hillel
    • G06F21/00G06F21/02
    • G06F21/10G06F21/725G06F2221/2137
    • A rights validator system for controlling access to content, the system including a query processor to receive a rights query and to provide a result to the rights query based on an estimated time, and a time-based query response module operationally connected to the query processor, the time-based query response module being operative to determine the estimated time as a function of a most recently updated time, and a plurality of indications of elapsed time since the most recently updated time, the indications of elapsed time being from a plurality of different sources of time indication. Related apparatus and methods are also included.
    • 用于控制对内容的访问的权限验证器系统,所述系统包括用于接收权限查询的查询处理器,并且基于估计的时间向所述权限查询提供结果;以及基于时间的查询响应模块,其操作地连接到所述查询处理器 基于时间的查询响应模块可操作以确定作为最近更新的时间的函数的估计时间,以及自最近更新的时间起经过的时间的多个指示,经过时间的指示来自多个 不同的时间指示来源。 还包括相关的装置和方法。