会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明申请
    • CIRCUIT AND METHOD FOR DYNAMICALLY ADJUSTING A FILTER BANDWIDTH
    • 用于动态调整滤波器带宽的电路和方法
    • WO2006071508A2
    • 2006-07-06
    • PCT/US2005/044974
    • 2005-12-13
    • FREESCALE SEMICONDUCTOR, INC.JOHNSON, Terence, L.MILLER, Timothy, R.
    • JOHNSON, Terence, L.MILLER, Timothy, R.
    • H03D3/24
    • H03L7/093H03D13/00H03L7/0991H04L7/0004H04L7/033
    • A tracking circuit (100) is provided for controlling a locally-generated clock. A receive channel (110) in the tracking circuit receives an incoming signal and a local clock, generates a local signal based on the local clock, and compares the local signal and the incoming signal to generate a data signal and an unfiltered phase error signal. A loop filter (120) filters the unfiltered phase error signal to provide a filtered phase error signal. A numerically controlled oscillator (140) generates a correction clock based on the filtered phase error signal. And a filter control circuit (160) provides one or more filter control signals to control operational parameters of the loop filter. The correction clock is provided to the receive channel to modify at least one of the phase and frequency of the local clock. In addition, a sample switch (125) may also be provided to sample the unfiltered phase error signal.
    • 提供跟踪电路(100)用于控制本地产生的时钟。 跟踪电路中的接收通道(110)接收输入信号和本地时钟,基于本地时钟产生本地信号,并且比较本地信号和输入信号以产生数据信号和未滤波的相位误差信号。 环路滤波器(120)对未滤波的相位误差信号进行滤波以提供滤波的相位误差信号。 数控振荡器(140)基于滤波的相位误差信号产生校正时钟。 并且滤波器控制电路(160)提供一个或多个滤波器控制信号以控制环路滤波器的操作参数。 校正时钟被提供给接收通道以修改本地时钟的相位和频率中的至少一个。 此外,还可以提供采样开关(125)以对未滤波的相位误差信号进行采样。
    • 5. 发明申请
    • SYSTEM AND METHOD FOR DETERMINING SIGNAL PHASE
    • 用于确定信号相的系统和方法
    • WO2008121567A1
    • 2008-10-09
    • PCT/US2008/057597
    • 2008-03-20
    • FREESCALE SEMICONDUCTOR INC.MILLER, Timothy, R.
    • MILLER, Timothy, R.
    • H04B1/40
    • H04L7/007
    • A receiver circuit (200) is provided, comprising: an agile clock (250) configured to generate an agile clock signal having a controllable agile clock phase based on agile clock control signals; a code processor (260) configured to receive an incoming signal and the agile clock signal, and to generate an on-time signal (110) and an error signal (120) corresponding to the incoming signal; a coarse acquisition circuit (270, 310) configured to identify a coarse acquisition phase based on a total power of the on-time signal and plus a total power of the error signal; a fine acquisition circuit (270, 320) configured to identify a fine acquisition phase based on the coarse acquisition phase and a magnitude of the on-time signal; and an acquisition controller (270, 330) configured to control operation of the coarse acquisition circuit and the fine acquisition circuit, and to provide a final acquisition phase as a current phase based on the one or more fine acquisition phases.
    • 提供了一种接收机电路(200),包括:敏捷时钟(250),被配置为基于敏捷时钟控制信号产生具有可控敏捷时钟相位的敏捷时钟信号; 配置成接收输入信号和敏捷时钟信号并产生对应于输入信号的接通时间信号(110)和误差信号(120)的代码处理器(260) 被配置为基于接通时间信号的总功率识别粗略采集相位并加上误差信号的总功率的粗略采集电路(270,310) 配置为基于所述粗略获取相位和所述接通时间信号的大小来识别精细采集相位的精细采集电路(270,320); 以及被配置为控制粗略采集电路和精细采集电路的操作的采集控制器(270,330),并且基于所述一个或多个精细采集阶段来提供作为当前阶段的最终采集阶段。
    • 6. 发明申请
    • SYSTEM AND METHOD FOR USING PROGRAMMABLE FREQUENCY OFFSETS IN A DATA NETWORK
    • 在数据网络中使用可编程频率偏移的系统和方法
    • WO2006060267A2
    • 2006-06-08
    • PCT/US2005/042627
    • 2005-11-22
    • FREESCALE SEMICONDUCTOR, INC.MCCORKLE, John, W.MILLER, Timothy, R.
    • MCCORKLE, John, W.MILLER, Timothy, R.
    • H04L7/00
    • H04L27/0014H03B21/00H03B2200/0078H04B1/7183H04L2007/047H04L2027/0016
    • A method is provided for offsetting a reference frequency of a quadrature reference clock signal. A quadrature reference clock (110) generates the quadrature reference clock signal at the reference frequency, while a quadrature variable offset clock (130) generates a quadrature clock signal at a base offset frequency based on a base offset value it receives from a control circuit (560). The base offset value can be determined in many ways, including reading it from a local memory (910) or receiving it from a remote device (1010). A polyphase mixer (140) performs a polyphase mixing operation between the quadrature reference clock signal and the offset clock signal to generate an agile clock signal having an agile clock frequency equal to the reference frequency plus the base offset frequency. If desired, the method can revise the offset frequency based on actual conditions and determine a corresponding revised offset value (920, 1020).
    • 提供了一种用于抵消正交参考时钟信号的参考频率的方法。 正交参考时钟(110)以参考频率产生正交参考时钟信号,而正交可变偏移时钟(130)基于从控制电路接收的基本偏移值以基本偏移频率产生正交时钟信号( 560)。 基本偏移值可以以许多方式确定,包括从本地存储器(910)读取或从远程设备(1010)接收基本偏移值。 多相混合器(140)在正交参考时钟信号和偏移时钟信号之间执行多相混合操作,以产生具有等于参考频率加上基极偏移频率的敏捷时钟频率的敏捷时钟信号。 如果需要,该方法可以根据实际条件修改偏移频率,并确定对应的修正偏移值(920,1020)。