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1. 发明申请

WO2014081860A3 PRIORITY-ASSIGNMENT INTERFACE TO ENHANCE APPROXIMATE COMPUTING 审中-公开
标题翻译：优先配置接口增强近似计算
公开(公告)号：WO2014081860A3
公开(公告)日：2014-10-30
申请号：PCT/US2013071063
申请日：2013-11-20
申请人： MICROSOFT CORP
发明人： STRAUSS KARIN , SAMPSON ADRIAN , CEZE LUIS HENRIQUE
IPC分类号： G06F17/10 , G06F9/46
CPC分类号： G06F9/46 , G06F11/10 , G06F11/1044 , G06F11/1666 , G06F17/10
摘要： A system and method are provided for enhancing approximate computing by a computer system. In one example, an interface is provided comprising a variable-identifier module and a bit-priority module. The variable-identifier module is configured to identify one or more variables of data that are to be processed by the computer system with approximate precision. Approximate precision is a precision level at which a hardware device does not guarantee full data-correctness for the one or more variables. The bit-priority module is configured to assign bit-priorities to the one or more variables. The bit-priorities include relative levels of importance among bits of each of the one or more variables. The relative levels of importance include at least high-priority bits and low-priority bits.
摘要翻译：提供了一种用于增强计算机系统的近似计算的系统和方法。在一个示例中，提供了包括可变标识符模块和位优先级模块的接口。可变标识符模块被配置为以近似精度来识别计算机系统要处理的数据的一个或多个变量。近似精度是硬件设备不能保证一个或多个变量的完整数据正确性的精度级别。位优先级模块被配置为为一个或多个变量分配比特优先级。位优先级包括一个或多个变量中的每一个的位之间的重要性的相对水平。相对的重要程度包括至少高优先级位和低优先级位。

2. 发明申请

WO2015031700A3 SPARSE MATRIX DATA STRUCTURE 审中-公开
标题翻译：稀疏矩阵数据结构
公开(公告)号：WO2015031700A3
公开(公告)日：2015-05-07
申请号：PCT/US2014053316
申请日：2014-08-29
申请人： MICROSOFT CORP
发明人： STRAUSS KARIN , FOWERS JEREMY , OVTCHAROV KALIN
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： Various embodiments relating to encoding a sparse matrix into a data structure format that may be efficiently processed via parallel processing of a computing system are provided. In one embodiment, a sparse matrix may be received. A set of designated rows of the sparse matrix may be traversed until all non-zero elements in the sparse matrix have been placed in a first array. Each time a row in the set is traversed, a next non-zero element in that row may be placed in the first array. If all non-zero elements for a given row of the set of designated rows have been placed in the first array, the given row may be replaced in the set of designated rows with a next unprocessed row of the sparse matrix. The data structure in which the sparse matrix is encoded may be outputted. The data structure may include the first array.
摘要翻译：提供了关于将稀疏矩阵编码为可以经由计算系统的并行处理有效地处理的数据结构格式的各种实施例。在一个实施例中，可以接收稀疏矩阵。可以遍历稀疏矩阵的指定行的集合，直到稀疏矩阵中的所有非零元素已经被放置在第一阵列中。每次遍历该集合中的一行时，该行中的下一个非零元素可以被放置在第一个阵列中。如果该组指定行的给定行的所有非零元素已经被放置在第一数组中，那么给定行可以在该组指定行中被替换为稀疏矩阵的下一个未处理行。可以输出稀疏矩阵被编码的数据结构。数据结构可以包括第一个阵列。

3. 发明申请

WO2015013153A3 SELF-IDENTIFYING MEMORY ERRORS 审中-公开
标题翻译：自我识别内存错误
公开(公告)号：WO2015013153A3
公开(公告)日：2015-06-25
申请号：PCT/US2014047345
申请日：2014-07-21
申请人： MICROSOFT CORP
发明人： DAVIS JOHN D , STRAUSS KARIN , MANASSE MARK STEVEN , GOPALAN PARIKSHIT S , YEKHANIN SERGEY
IPC分类号： G11C29/52 , G11C13/00 , G11C16/34 , G11C29/44
CPC分类号： G11C29/4401 , G11C13/0033 , G11C13/0035 , G11C13/0064 , G11C16/3404 , G11C16/3454 , G11C16/349 , G11C29/52 , G11C2029/0409
摘要： A memory region can durably self-identify itself as being faulty when read. Information that would have been assigned to the faulty memory region can be assigned to another of that sized region in memory using a replacement encoding technique. For phase change memory, at least two fault states can be provided for durably self- identifying a faulty memory region; one state at a highest resistance range and the other state at a lowest resistance range. Replacement cells can be used to shift or assign data when a self-identifying memory fault is present. A memory controller and memory module, alone or in combination, may manage replacement cell use and facilitate driving a newly discovered faulty cell to a fault state if the faulty cell is not already at the fault state.
摘要翻译：存储区可以在读取时耐久地自我识别为有缺陷。可以使用替换编码技术将分配给故障存储器区域的信息分配给存储器中的该大小区域中的另一个。对于相变存储器，可以提供至少两个故障状态以持久地自我识别故障存储器区域; 一个状态处于最高电阻范围，另一个状态处于最低电阻范围。当存在自我识别的存储器故障时，替换单元可用于移位或分配数据。单独或组合的存储器控制器和存储器模块可以管理替换单元的使用，并且如果故障单元尚未处于故障状态，便于将新发现的故障单元驱动到故障状态。

4. 发明申请

WO2012109631A3 REMOTE CORE OPERATIONS IN A MULTI-CORE COMPUTER 审中-公开
标题翻译：远程核心操作在多核心计算机
公开(公告)号：WO2012109631A3
公开(公告)日：2012-10-18
申请号：PCT/US2012024776
申请日：2012-02-11
申请人： MICROSOFT CORP
发明人： BLACK RICHARD JOHN , HARRIS TIMOTHY , MCILROY ROSS CAMERON , STRAUSS KARIN
IPC分类号： G06F15/80 , G06F13/14 , G06F15/167
CPC分类号： G06F15/167 , G06F12/0802 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0866
摘要： A multi-core processor with a shared physical memory is described. In an embodiment a sending core sends a memory write request to a destination core so that the request may be acted upon by the destination core as if it originated from the destination core. In an example, a data structure is configured in the shared physical memory and mapped to be accessible to the sending and destination cores. In an example, the shared data structure is used as a message channel between the sending and destination cores to carry data using the memory write request. In an embodiment a notification mechanism is enabled using the shared physical memory in order to notify the destination core of events by updating a notification data structure. In an example, the notification mechanism triggers a notification process at the destination core to inform a receiving process of a notification.
摘要翻译：描述了具有共享物理内存的多核处理器。在一个实施例中，发送核心向目的地核心发送存储器写入请求，使得请求可以被目的地核心作为来自目的地核心的动作。在一个示例中，在共享物理内存中配置数据结构，并将其映射到发送和目标内核可访问。在一个示例中，共享数据结构被用作发送和目的地核心之间的消息通道，以使用存储器写入请求来携带数据。在一个实施例中，使用共享物理存储器启用通知机制，以通过更新通知数据结构来通知目的地核心的事件。在一个示例中，通知机制触发目的地核心处的通知处理，以通知接收进程通知。

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