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1. 发明申请

WO2006101695A1 PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES 审中-公开
标题翻译：相对于光刻特征的PITCH减少图案
公开(公告)号：WO2006101695A1
公开(公告)日：2006-09-28
申请号：PCT/US2006/007739
申请日：2006-03-03
申请人： MICRON TECHNOLOGY, INC. , TRAN, Luan , RERICHA, William, T. , LEE, John , ALAPATI, Ramakanth , HONARKHAH, Sheron , MENG, Shuang , SHARMA, Puneet , BAI, Jingyi , YIN, Zhiping , MORGAN, Paul , ABATCHEV, Mirzafer, K. , SANDHU, Gurtej, S. , DURCAN, D. Mark
发明人： TRAN, Luan , RERICHA, William, T. , LEE, John , ALAPATI, Ramakanth , HONARKHAH, Sheron , MENG, Shuang , SHARMA, Puneet , BAI, Jingyi , YIN, Zhiping , MORGAN, Paul , ABATCHEV, Mirzafer, K. , SANDHU, Gurtej, S. , DURCAN, D. Mark
IPC分类号： H01L21/033 , H01L21/308
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit (100) are formed by etching a substrate (110) using a mask which is formed by combining two separately formed patterns (177) and (230). Pitch multiplication is used to form the relatively small features (175) of the first pattern (177) and conventional photolithography used to form the relatively large features of the second pattern (230). Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers (175) are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers (175), which define the first mask pattern (177). A bottom anti-reflective coating (BARC) is then deposited around the spacers (175) to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern (230), which is then is transferred to the BARC. The combined pattern (177, 230) made out by the first pattern (177) and the second pattern (230) is transferred to an underlying amorphous silicon layer (150) and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern (177, 230) is then transferred to the silicon oxide layer (155) and then to an amorphous carbon mask layer (160). The combined mask pattern (177, 230), having features of difference sizes, is then etched into the underlying substrate (110) through the amorphous carbon hard mask layer (160).
摘要翻译：通过使用通过组合两个分开形成的图案（177）和（230）而形成的掩模蚀刻衬底（110）来形成集成电路（100）的不同尺寸的特征。间距倍增用于形成第一图案（177）的较小特征（175）和用于形成第二图案（230）的较大特征的常规光刻。间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。然后在无定形碳的侧壁上形成侧壁间隔物（175）。去除无定形碳，留下限定第一掩模图案（177）的侧壁间隔物（175）。然后将底部抗反射涂层（BARC）沉积在间隔物（175）周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案（230），然后将其转印到BARC。由第一图案（177）和第二图案（230）制成的组合图案（177,230）被转印到下面的非晶硅层（150），并且图案经受碳带以去除BARC和光刻胶材料。然后将组合图案（177,230）转移到氧化硅层（155），然后转移到无定形碳掩模层（160）。具有不同尺寸特征的组合掩模图案（177,230）然后通过无定形碳硬掩模层（160）蚀刻到下面的衬底（110）中。

2. 发明申请

WO2006026699A2 METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION 审中-公开
标题翻译：使用PITCH MULTIPLICATION的集成电路制造方法
公开(公告)号：WO2006026699A2
公开(公告)日：2006-03-09
申请号：PCT/US2005/031094
申请日：2005-08-26
申请人： MICRON TECHNOLOGY, INC. , ABATCHEV, Mirzafer, K. , SANDHU, Gurtej , TRAN, Luan , RERICHA, William, T. , DURCAN, Mark, D.
发明人： ABATCHEV, Mirzafer, K. , SANDHU, Gurtej , TRAN, Luan , RERICHA, William, T. , DURCAN, Mark, D.
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , Y10S438/947 , Y10S438/95
摘要： Different sized features in the array 102 and in the periphery 104 of an integrated circuit 100 are patterned on a substrate 110 in a single step. In particular, a mixed pattern, combining two separately formed patterns 177, 230, is formed on a single mask layer 160 and then transferred to the underlying substrate 110. The first of the separately formed patterns, 177, is formed by pitch multiplication and the second of the separately formed patterns, 230, is formed by conventional photolithography. The first of the separately formed patterns, 177, includes features 175 that are below the resolution of the photolithographic process used to form the second of the separately formed patterns, 230. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers 175 having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers 175 to form the mask pattern 177. Thus, the spacers 175 form the mask 177 having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material 200 is deposited around the spacers 175. The spacers 175 are further protected using a hard mask 210 and then photoresist 220 is formed and patterned over the hard mask 210. The photoresist pattern 230 is transferred through the hard mask 210 to the protective material 200. The combination of the patterns 177 and 230 made out by the spacers 175 and the protective material 200 is then transferred to an underlying amorphous carbon hard mask layer 160. The combined pattern, having features of difference sizes, is then transferred to the underlying substrate 110.
摘要翻译：阵列102中和集成电路100的周边104中的不同尺寸的特征在单个步骤中在衬底110上图案化。特别地，组合两个单独形成的图案177,230的混合图案形成在单个掩模层160上，然后转移到下面的衬底110.单独形成的图案177中的第一个由间距倍增形成，并且通过常规光刻法形成分开形成的图案230的第二个。单独形成的图案177中的第一个包括低于用于形成第二个单独形成的图案230的光刻工艺的分辨率的特征175.这些线通过在光致抗蚀剂上形成图案然后蚀刻该图案成为无定形碳层。在无定形碳的侧壁上形成宽度小于无定形碳的未蚀刻部分的宽度的侧壁夹具175。然后去除无定形碳，留下侧壁间隔物175以形成掩模图案177.因此，间隔物175形成具有小于用于在光致抗蚀剂上形成图案的光刻工艺的分辨率的特征尺寸的掩模177。保护材料200沉积在间隔物175周围。使用硬掩模210进一步保护间隔物175，然后在硬掩模210上形成并图案化光致抗蚀剂220.光致抗蚀剂图案230通过硬掩模210转移到保护层然后将由间隔物175和保护材料200制成的图案177和230的组合转移到下面的无定形碳硬掩模层160.然后将具有不同尺寸特征的组合图案转移到底层衬底110。

3. 发明申请

WO2008027876A3 SEMICONDUCTOR DEVICES INCLUDING FINE PITCH ARRAYS WITH STAGGERED CONTACTS AND METHODS FOR DESIGNING AND FABRICATING THE SAME 审中-公开
公开(公告)号：WO2008027876A3
公开(公告)日：2008-03-06
申请号：PCT/US2007/076970
申请日：2007-08-28
申请人： MICRON TECHNOLOGY, INC. , LEE, John K. , KIM, Hyuntae , STOCKS, Richard L. , TRAN, Luan
发明人： LEE, John K. , KIM, Hyuntae , STOCKS, Richard L. , TRAN, Luan
IPC分类号： H01L21/8242
摘要： A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one or both of misalignment during fabrication of the contacts and contact resistance between sections of the contacts. The contacts of one row communicate with every other active-device region and are staggered relative to the contacts of another row, which communicate with the remaining active-device regions. Each contact may include a relatively large contact plug with a relatively large upper surface to provide a relatively large amount of tolerance as a contact hole for an upper portion of the contact is formed. The contact holes may be formed substantially simultaneously with trenches for conductive traces, such as bit lines, in a dual damascene process. Intermediate structures are also disclosed, as are methods for designing semiconductor device structures.

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