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1. 发明申请

WO2021006989A1 MEMORY CELLS AND METHODS OF FORMING A CAPACITOR INCLUDING CURRENT LEAKAGE PATHS HAVING DIFFERENT TOTAL RESISTANCES 审中-公开
公开(公告)号：WO2021006989A1
公开(公告)日：2021-01-14
申请号：PCT/US2020/037261
申请日：2020-06-11
申请人： MICRON TECHNOLOGY, INC.
发明人： MUTCH, Michael , CHAVAN, Ashonita, A. , CHHAJED, Sameer , COOK, Beth, R. , MUTHUKRISHNAN, Kamal, Kumar , RAMASWAMY, Durai, Vishak, Nirmal , WILLIAMSON, Lance
IPC分类号： H01L27/11507 , H01L49/02 , G11C11/221 , H01L27/11502 , H01L28/55 , H01L28/60 , H01L28/90
摘要： A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

2. 发明申请

WO2021030127A1 TRANSISTOR AND METHODS OF FORMING TRANSISTORS 审中-公开
公开(公告)号：WO2021030127A1
公开(公告)日：2021-02-18
申请号：PCT/US2020/045103
申请日：2020-08-06
申请人： MICRON TECHNOLOGY, INC.
发明人： NAHAR, Manuj , ANTONOV, Vassil, N. , KARDA, Kamal, M. , MUTCH, Michael , LIU, Hung-wei , HULL, Jeffery, B.
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L29/10 , H01L29/08 , H01L29/16 , H01L21/02
摘要： A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally- adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically -elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

3. 发明申请

WO2021252128A1 METHODS OF INCORPORATING LEAKER DEVICES INTO CAPACITOR CONFIGURATIONS TO REDUCE CELL DISTURB, AND CAPACITOR CONFIGURATIONS INCORPORATING LEAKER DEVICES 审中-公开
公开(公告)号：WO2021252128A1
公开(公告)日：2021-12-16
申请号：PCT/US2021/032336
申请日：2021-05-13
申请人： MICRON TECHNOLOGY, INC.
发明人： MUTCH, Michael , KELKAR, Sanket, S. , CHAVAN, Ashonita, A. , CHHAJED, Sameer , JEBARAJ, Adriel Jebin, Jacob
IPC分类号： H01L49/02 , H01L27/11507 , G11C11/22 , G11C11/4091 , G11C11/4096 , H01L27/11504 , H01L27/11587 , H01L27/1159 , H01L28/56
摘要： Some embodiments include a capacitor having a container- shaped bottom portion. The bottom portion has a first region over a second region. The first region is thinner than the second region. The first region is a leaker region and the second region is a bottom electrode region. The bottom portion has an interior surface that extends along the first and second regions. An insulative material extends into the container shape. The insulative material lines the interior surface of the container shape. A conductive plug extends into the container shape and is adjacent the insulative material. A conductive structure extends across the conductive plug, the insulative material and the first region of the bottom portion. The conductive structure directly contacts the insulative material and the first region of the bottom portion, and is electrically coupled with the conductive plug. Some embodiments include methods of forming assemblies.

4. 发明申请

WO2021030078A1 TRANSISTOR AND METHODS OF FORMING TRANSISTORS 审中-公开
公开(公告)号：WO2021030078A1
公开(公告)日：2021-02-18
申请号：PCT/US2020/044509
申请日：2020-07-31
申请人： MICRON TECHNOLOGY, INC.
发明人： NAHAR, Manuj , MUTCH, Michael
IPC分类号： H01L29/78 , H01L29/10 , H01L29/08 , H01L29/423 , H01L29/66 , H01L21/268
摘要： A transistor comprises a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions. A gate is operatively laterally-adjacent the channel region. The top source/drain region, the bottom source/drain region, and the channel region respectively have crystal grains and grain boundaries between immediately- adjacent of the crystal grains. At least one of the bottom source/drain region and the channel region has an internal interface there-within between the crystal grains that are above the internal interface and the crystal grains that are below the internal interface. At least some of the crystal grains that are immediately- above the internal interface physically contact at least some of the crystal grains that are immediately- below the internal interface. All of the grain boundaries that are between immediately-adjacent of the physically-contacting crystal grains that are immediately -above and that are immediately-below the interface align relative one another. The internal interface comprises at least one of (a) and (b), where (a): conductivity-modifying dopant concentration immediately -above the internal interface is lower than immediately-below the internal interface and (b): a laterally -discontinuous insulative oxide. Other embodiments, including method, are disclosed.

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