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1. 发明申请

WO2019173649A1 PROVIDING DATA OF A MEMORY SYSTEM BASED ON AN ADJUSTABLE ERROR RATE 审中-公开
公开(公告)号：WO2019173649A1
公开(公告)日：2019-09-12
申请号：PCT/US2019/021239
申请日：2019-03-07
申请人： MICRON TECHNOLOGY, INC.
发明人： KOUDELE, Larry J. , KAYNAK, Mustafa N. , SHEPEREK, Michael , KHAYAT, Patrick R. , RATNAM, Sampath K.
IPC分类号： G06F3/06
摘要： A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation in response to determining that the first error rate exceeds the threshold.

2. 发明申请

WO2019157369A1 PROVIDING RECOVERED DATA TO A NEW MEMORY CELL AT A MEMORY SUB-SYSTEM BASED ON AN UNSUCCESSFUL ERROR CORRECTION OPERATION 审中-公开
公开(公告)号：WO2019157369A1
公开(公告)日：2019-08-15
申请号：PCT/US2019/017333
申请日：2019-02-08
申请人： MICRON TECHNOLOGY, INC.
发明人： RATNAM, Sampath K. , RAYAPROLU, Vamsi Pavan , KAYNAK, Mustafa N. , PARTHASARATHY, Sivagnanam , MUCHHERLA, Kishore Kumar , NOWELL, Shane , FEELEY, Peter , LIN, Qisong
IPC分类号： G06F11/16 , G06F3/06
摘要： At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data i s provided to the other memory cell of the memory component.

3. 发明申请

WO2019156909A1 MITIGATING A VOLTAGE CONDITION OF A MEMORY CELL IN A MEMORY SUB-SYSTEM 审中-公开
公开(公告)号：WO2019156909A1
公开(公告)日：2019-08-15
申请号：PCT/US2019/016421
申请日：2019-02-01
申请人： MICRON TECHNOLOGY, INC.
发明人： MUCHHERLA, Kishore Kumar , RAYAPROLU, Vamsi Pavan , FEELEY, Peter , RATNAM, Sampath K. , PARTHASARATHY, Sivagnanam , LIN, Qisong , NOWELL, Shane , KAYNAK, Mustafa N.
IPC分类号： G11C29/52 , G11C29/02 , G06F11/10
摘要： A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

4. 发明申请

WO2019173534A1 ADJUSTING A PARAMETER FOR A PROGRAMMING OPERATION BASED ON THE TEMPERATURE OF A MEMORY SYSTEM 审中-公开
公开(公告)号：WO2019173534A1
公开(公告)日：2019-09-12
申请号：PCT/US2019/021039
申请日：2019-03-06
申请人： MICRON TECHNOLOGY, INC.
发明人： KAYNAK, Mustafa N. , RATNAM, Sampath K. , LOH, Zixiang , RAO, Nagendra Prasad Ganesh , KOUDELE, Larry J. , RAYAPROLU, Vamsi Pavan , KHAYAT, Patrick R. , NOWELL, Shane
IPC分类号： G11C7/04 , G11C16/10 , G06F11/10 , G06F3/06
摘要： A temperature related to a memory device is identified. It is determined whether the temperature related to the memory device satisfies a threshold temperature condition. Responsive to detecting that the temperature related to the memory device satisfies the threshold temperature condition, a parameter for a programming operation is adjusted from a first value to a second value to store data at the memory device.

5. 发明申请

WO2019157216A1 PERFORMING AN OPERATION ON A MEMORY CELL OF A MEMORY SYSTEM AT A FREQUENCY BASED ON TEMPERATURE 审中-公开
公开(公告)号：WO2019157216A1
公开(公告)日：2019-08-15
申请号：PCT/US2019/017104
申请日：2019-02-07
申请人： MICRON TECHNOLOGY, INC.
发明人： RATNAM, Sampath K. , RAYAPROLU, Vamsi Pavan , KAYNAK, Mustafa N. , FEELEY, Peter , MUCHHERLA, Kishore Kumar , PADILLA, Renato C. , NOWELL, Shane
IPC分类号： G11C7/04 , G11C16/08 , G06F11/00
摘要： A temperature associated with the memory component is determined. A frequency to perform an operation on a memory cell associated with the memory component is determined based on the temperature associated with the memory component. The operation is performed on the memory cell at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.

6. 发明申请

WO2017180289A1 MONITORING ERROR CORRECTION OPERATIONS PERFORMED IN MEMORY 审中-公开
标题翻译：监视存储器中执行的错误纠正操作
公开(公告)号：WO2017180289A1
公开(公告)日：2017-10-19
申请号：PCT/US2017/022897
申请日：2017-03-17
申请人： MICRON TECHNOLOGY, INC.
发明人： KAYNAK, Mustafa N. , KHAYAT, Patrick R. , PARTHASARATHY, Sivagnanam
IPC分类号： G06F11/10
摘要： The present disclosure includes apparatuses and methods for monitoring error correction operations performed in memory. A number of embodiments include a memory and circuitry configured to determine a quantity of erroneous data corrected during an error correction operation performed on soft data associated with a sensed data state of a number of memory cells of the memory, determine a quality of soft information associated with the erroneous data corrected during the error correction operation performed on the soft data, and determine whether to take a corrective action on the sensed data based on the quantity of the erroneous data corrected during the error correction operation and the quality of the soft information associated with the erroneous data corrected during the error correction operation.
摘要翻译：本公开包括用于监视在存储器中执行的纠错操作的装置和方法。许多实施例包括存储器和电路，其被配置为确定在对与存储器的多个存储器单元的感测数据状态相关联的软数据执行的错误校正操作期间校正的错误数据的量，确定关联的软信息的质量在对软数据执行错误校正操作期间校正错误数据，并且基于在错误校正操作期间校正的错误数据的数量和关联的软信息的质量来确定是否对感测数据进行校正动作在纠错操作期间纠正了错误的数据。

7. 发明申请

WO2014022518A1 MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES 审中-公开
标题翻译：在相邻数据状态之间的谷中的存储单元状态
公开(公告)号：WO2014022518A1
公开(公告)日：2014-02-06
申请号：PCT/US2013/052942
申请日：2013-07-31
申请人： MICRON TECHNOLOGY, INC.
发明人： PARTHASARATHY, Sivagnanam , KHAYAT, Patrick R. , KAYNAK, Mustafa N. , EISENHUTH, Robert B.
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C11/5642 , G06F11/1048 , G06F11/1068 , G06F11/1072 , G11C16/0483 , G11C16/06 , G11C16/26 , G11C16/3418 , G11C29/52
摘要： The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley.
摘要翻译：本公开包括与相邻数据状态之间的谷中的存储器单元状态有关的装置和方法。多种方法可以包括确定存储器单元的状态是否处于与相应数据状态相关联的状态的相邻分布之间的谷内。该方法还可以包括发送指示存储器单元的数据状态的信号以及存储单元的状态是否在谷中。

8. 发明申请

WO2018169764A1 TIERED ERROR CORRECTION CODE (ECC) OPERATIONS IN MEMORY 审中-公开
公开(公告)号：WO2018169764A1
公开(公告)日：2018-09-20
申请号：PCT/US2018/021639
申请日：2018-03-09
申请人： MICRON TECHNOLOGY, INC.
发明人： KAYNAK, Mustafa N. , KHAYAT, Patrick R. , PARTHASARATHY, Sivagnanam
IPC分类号： G06F11/10
摘要： Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.

9. 发明申请

WO2018052667A1 APPARATUSES AND METHODS FOR GENERATING PROBABILISTIC INFORMATION WITH CURRENT INTEGRATION SENSING 审中-公开
标题翻译：利用电流积分传感产生概率信息的装置和方法
公开(公告)号：WO2018052667A1
公开(公告)日：2018-03-22
申请号：PCT/US2017/047925
申请日：2017-08-22
申请人： MICRON TECHNOLOGY, INC.
发明人： KHAYAT, Patrick R. , PARTHASARATHY, Sivagnanam , KAYNAK, Mustafa N. , HELM, Mark A. , YIP, Aaron S.
IPC分类号： G11C16/26 , G11C16/34
摘要： Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.
摘要翻译：公开了用于使用电流积分产生用于误差校正的概率信息的方法和装置。一种示例方法包括：响应于感测第一多个单元，基于第一感测阈值感测第一多个存储器单元;将第一组概率信息与第一多个存储器单元相关联;感测基于第二多个存储器单元的第二多个存储器单元在第二感测阈值上，响应于感测所述第二多个存储器单元，将第二组概率信息与所述第二多个存储器单元相关联，并且对所述第一和第二多个存储器单元执行错误校正操作，至少基于部分取决于第一个和第二个值。

10. 发明申请

WO2018052652A1 APPARATUSES AND METHODS FOR STAIRCASE CODE ENCODING AND DECODING FOR STORAGE DEVICES 审中-公开
标题翻译：用于存储设备的阶梯代码编码和解码的装置和方法
公开(公告)号：WO2018052652A1
公开(公告)日：2018-03-22
申请号：PCT/US2017/047530
申请日：2017-08-18
申请人： MICRON TECHNOLOGY, INC.
发明人： KHAYAT, Patrick R. , PARTHASARATHY, Sivagnanam , KAYNAK, Mustafa N.
IPC分类号： H03M13/11 , H03M13/15
摘要： An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.
摘要翻译：提供了一种装置。该装置包括第一校正子计算电路，其被配置为接收具有多个行和多个列的码字，并且还被配置为计算码字的第一分量码字的至少一部分的第一校正子。该设备还包括第二校正子计算电路，其被配置为接收码字并且计算码字的第二分量码字的至少一部分的第二校正子。该设备还包括比特校正电路，该比特校正电路被配置为至少部分地基于第一和第二校正子中的至少一个来校正码字中的一个或多个错误比特，其中第一和第二分量码字跨越两行或更多行以及两个或更多的码字列。

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