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1. 发明申请

WO2020263373A1 SECURITY OF EMBEDDED DEVICES THROUGH A DEVICE LIFECYCLE WITH A DEVICE IDENTIFIER 审中-公开
公开(公告)号：WO2020263373A1
公开(公告)日：2020-12-30
申请号：PCT/US2020/024854
申请日：2020-03-26
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SIMMONS, Michael
IPC分类号： G06F21/72 , G01R31/317
摘要： An apparatus includes a database with device profiles, and a device programmer. The device programmer includes instructions. The instructions, when read and executed by a processor, cause the device programmer to identify a device identifier of an electronic device. The device programmer is further caused to, based upon the device identifier, access device data from the database. The device programmer is further caused to, based upon the device data, determine an area of memory of the electronic device that can be written. The device programmer is further caused to, based on the determination of the area of memory of the electronic device that can be written, write data to the area of memory.

2. 发明申请

WO2013126422A1 CRYPTOGRAPHIC TRANSMISSION SYSTEM USING KEY ENCRYPTION KEY 审中-公开
标题翻译：使用关键加密键的光栅传输系统
公开(公告)号：WO2013126422A1
公开(公告)日：2013-08-29
申请号：PCT/US2013/026891
申请日：2013-02-20
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SIMMONS, Michael
IPC分类号： H04L9/08
CPC分类号： G06F12/1408 , G06F21/00 , G06F21/602 , G06F21/606 , G06F21/72 , G06F2221/2113 , H04L9/0822
摘要： A microcontroller includes on-chip key storage slots stored in a non-volatile memory, wherein selecting which key is to be used is restricted to software, wherein a predetermined key storage slot stores a Key Encrypt Key (KEK), and a register flag is provided for determining whether the predetermined key storage slot stores a key for encrypting/decrypting data or the KEK for encrypting/decrypting a key
摘要翻译：微控制器包括存储在非易失性存储器中的片上密钥存储时隙，其中选择要使用的密钥是限于软件，其中预定的密钥存储时隙存储密钥加密密钥（KEK），寄存器标志是用于确定预定密钥存储时隙是否存储用于加密/解密数据的密钥或用于加密/解密密钥的KEK

3. 发明申请

WO2008073883A2 MAINTAINING INPUT AND/OR OUTPUT CONFIGURATION AND DATA STATE DURING AND WHEN COMING OUT OF A LOW POWER MODE 审中-公开
标题翻译：维持输入和/或输出配置和数据状态在低功耗模式下
公开(公告)号：WO2008073883A2
公开(公告)日：2008-06-19
申请号：PCT/US2007/086963
申请日：2007-12-10
申请人： MICROCHIP TECHNOLOGY INCORPORATED , SIMMONS, Michael , WOJEWODA, Igor
发明人： SIMMONS, Michael , WOJEWODA, Igor
IPC分类号： H03K19/00
CPC分类号： G06F1/3203 , G06F1/24
摘要： A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a "low power state wake-up and restore" signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.
摘要翻译：半导体集成电路器件在从低功率模式退出时，唤醒并重新初始化逻辑电路，以便恢复内部寄存器的先前逻辑状态，而不会干扰当前存在的输入输出（I / O）配置控制和数据状态输入低功耗模式。因此，在低功率模式下，不能分配连接到半导体集成电路器件的其它器件的操作。一旦半导体集成电路器件的所有内部逻辑和寄存器被重新初始化，就可能发出“低功率状态唤醒和恢复”信号。该信号表示在集成电路器件进入低功率模式时存储在I / O保持器单元中的I / O配置控制和数据状态已被恢复，并且可以将控制返回到逻辑电路和/或内部半导体集成电路器件的寄存器。

4. 发明申请

WO2019217166A1 MEMORY POOL ALLOCATION FOR A MULTI-CORE SYSTEM 审中-公开
公开(公告)号：WO2019217166A1
公开(公告)日：2019-11-14
申请号：PCT/US2019/030111
申请日：2019-05-01
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SIMMONS, Michael , SISTLA, Anjana Priya , GUPTA, Priyank
IPC分类号： G06F12/02
摘要： An apparatus includes processing cores, memory blocks, a connection between each of processing core and memory block, chip selection circuit, and chip selection circuit busses between the chip selection circuit and each of the memory blocks. Each memory block includes a data port and a memory check port. The chip selection circuit is configured to enable writing data from a highest priority core through respective data ports of the memory blocks. The chip selection circuit is further configured to enable writing data from other cores through respective memory check ports of the memory blocks.

5. 发明申请

WO2016153965A1 ONE TIME PROGRAMMABLE MEMORY 审中-公开
标题翻译：一次可编程内存
公开(公告)号：WO2016153965A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/023033
申请日：2016-03-18
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： PESAVENTO, Rodney , SIMMONS, Michael
IPC分类号： G11C17/18 , G11C7/10
CPC分类号： G11C17/16 , G11C7/1006 , G11C17/18 , G11C29/76 , G11C2211/5646 , G11C2211/5647
摘要： Systems and method for controlling the programming of a one-time programmable (OTP) memory are disclosed. The systems and methods include an OTP memory array comprising an array organized in lines of n+1 bit, wherein n is an integer number designating a word size of the OTP memory, wherein the additional bit indicates whether a memory line is stored in an inverted or non-inverted fashion, encoding logic configured determine whether a word is to be stored inverted or non-inverted, and decoding logic configured to decode a stored word and controlled by the additional bit indicating whether a word has been stored inverted or non-inverted.
摘要翻译：公开了一种用于控制一次性可编程（OTP）存储器的编程的系统和方法。该系统和方法包括一个OTP存储器阵列，其包括以n + 1位行的形式组织的阵列，其中n是指定OTP存储器的字大小的整数，其中附加位指示存储器线是否以倒置或非反转方式，配置的编码逻辑确定字是否被反转或非反相存储，以及解码逻辑，其被配置为对所存储的字进行解码并由附加位控制，指示字是否已被反转或非反相存储。

6. 发明申请

WO2013052334A1 VIRTUAL GENERAL PURPOSE INPUT/OUTPUT FOR A MICROCONTROLLER 审中-公开
标题翻译：虚拟通用输入/输出用于微控制器
公开(公告)号：WO2013052334A1
公开(公告)日：2013-04-11
申请号：PCT/US2012/057430
申请日：2012-09-27
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SIMMONS, Michael
IPC分类号： G06F13/40
CPC分类号： G06F13/4068
摘要： A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.
摘要翻译：微控制器包括具有耦合到多个外部引脚的多个位的通用输入/输出（GPIO）端口; 用于提供GPIO端口的第一控制和数据输入/输出功能中的至少一个的第一组寄存器; 第二组寄存器，用于提供GPIO端口的第二控制和数据输入/输出功能中的至少一个; 以及多路复用器和相关联的选择寄存器，用于控制多路复用器以通过所述第一或第二寄存器组来控制所述GPIO端口。

7. 发明申请

WO2009067685A2 ETHERNET CONTROLLER 审中-公开
标题翻译：以太网控制器
公开(公告)号：WO2009067685A2
公开(公告)日：2009-05-28
申请号：PCT/US2008/084382
申请日：2008-11-21
申请人： MICROCHIP TECHNOLOGY INCORPORATED , SIMMONS, Michael , SCHLUNDER, Howard, Henry
发明人： SIMMONS, Michael , SCHLUNDER, Howard, Henry
CPC分类号： H04L49/40 , H04L49/351
摘要： An Ethernet controller semiconductor chip has a system control unit, a media access control layer coupled with the system control unit, a physical layer coupled with the media access control layer, wherein the physical layer comprises a receiving port and a transmitting port, a switch control unit for providing a control signal for auto media device interface switching, and a plurality of external pins, wherein four pins are coupled with the receiving and transmitting port of the physical layer and one pin is coupled with the switch control unit for providing external access to the control signal for auto media device interface switching.
摘要翻译：以太网控制器半导体芯片具有系统控制单元，与系统控制单元耦合的媒体访问控制层，与媒体访问控制层耦合的物理层，其中物理层包括接收端口发送端口，用于提供用于自动媒体设备接口切换的控制信号的开关控制单元以及多个外部引脚，其中四个引脚与物理层的接收和发送端口耦合，并且一个引脚与开关控制单元，用于提供对用于自动媒体设备接口切换的控制信号的外部访问。

8. 发明申请

WO2008118933A1 LOW POWER MODE FAULT RECOVERY APPARATUS AND METHOD THEREFOR 审中-公开
标题翻译：低功耗模式故障恢复装置及其方法
公开(公告)号：WO2008118933A1
公开(公告)日：2008-10-02
申请号：PCT/US2008/058196
申请日：2008-03-26
申请人： MICROCHIP TECHNOLOGY INCORPORATED , SIMMONS, Michael
发明人： SIMMONS, Michael
IPC分类号： G06F11/16 , G06F1/32
CPC分类号： G06F1/3203 , G06F11/167
摘要： A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level before the integrated circuit device goes into a low power mode. An exclusive OR (XOR) is performed on the outputs of the two keeper cells (a keeper cell pair) such that if the two keeper cells of the keeper cell pair do not have opposite logic levels stored therein, then the respective XOR outputs an error signal for that keeper cell pair and the error signal is used to force the integrated circuit device out of the low power mode, depending on software control, with or without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered.
摘要翻译：半导体集成电路器件每个配置使用两个保持器单元和/或使能位作为具有错误检测的双冗余存储器。两个保持单元之一存储逻辑电平，另一个保持单元在集成电路器件进入低功率模式之前存储该逻辑电平的倒数。对两个保持单元（保持单元对）的输出执行异或（XOR），使得如果保持单元对的两个保持单元不具有存储在其中的相反逻辑电平，则相应的异或输出错误根据软件控制，使用该保持单元对的信号和误差信号强制集成电路设备脱离低功耗模式，具有或不具有干扰输入输出（I / O）配置控制和存在于时间输入低功耗模式。

9. 发明申请

WO2015073495A1 INTEGRATED CIRCUIT DEVICE WITH TAMPER DTECTION INPUT AND HAVING REAL TIME CLOCK AND CALENDAR LOGGING THEREOF 审中-公开
标题翻译：具有篡改输入并具有实时时钟和日历记录的集成电路设备
公开(公告)号：WO2015073495A1
公开(公告)日：2015-05-21
申请号：PCT/US2014/065150
申请日：2014-11-12
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： BOWLING, Stephen , SIMMONS, Michael
IPC分类号： G01R22/06 , G08B13/00
CPC分类号： H04Q9/00 , G01R22/066 , G08B13/00
摘要： If an enclosure of a metering device is opened or vandalized, application software must determine when the metering history information became unreliable, and further notification to the utility may be desirable. Likewise, a shipping container or suitcase that has been opened or mishandled during shipping transient may be attributed to a particular location and/or handling person(s) when the time and date of the mishandling occurrence are known. An input from a tamper or mishandling sensor (120) initiates capture of real¬ time clock/calendar (RTCC) information.
摘要翻译：如果计量设备的外壳打开或破坏，则应用软件必须确定测量历史信息何时变得不可靠，并且可能需要进一步通知公用程序。同样地，在运输过程中已经打开或处理不当的运输集装箱或手提箱可能会在处理不当的时间和日期已知时归属于特定的位置和/或处理人员。来自篡改或误操作传感器（120）的输入启动实时时钟/日历（RTCC）信息的捕捉。

10. 发明申请

WO2014149583A1 MINIMIZING SWITCHOVER TIME DURING OPERATING SYSTEM KERNEL UPDATE IN A HOT SWAPPABLE PROGRAM MEMORY 审中-公开
标题翻译：操作系统中最小化切换时间KERNEL更新在热插拔程序存储器
公开(公告)号：WO2014149583A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/019737
申请日：2014-03-01
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SIMMONS, Michael , WOJEWODA, Igor , SAMUEL, Roshan
IPC分类号： G06F9/445 , G06F9/44
CPC分类号： G06F1/24 , G06F8/656 , G06F9/4401 , G06F9/4406 , G06F9/4411 , G06F9/44505
摘要： A method for hot swapping an operating system kernel in a system, wherein the system comprises a central processing unit, one or more system components and a program memory including an old kernel and a new kernel, the method comprising: - configuring, by the old kernel, the system to boot from the new kernel by branching into a suitable entry point in the new kernel; - identifying, by the new kernel, one or more system components which require a reinitialization or reset; - further executing the new kernel in order to reinitialize or reset the one or more system components.
摘要翻译：一种用于热交换系统中的操作系统内核的方法，其中所述系统包括中央处理单元，一个或多个系统组件以及包括旧内核和新内核的程序存储器，所述方法包括： - 由旧的内核，系统通过分支到新内核中的合适入口点从新内核引导; - 由新内核识别需要重新初始化或重置的一个或多个系统组件; - 进一步执行新内核以重新初始化或重置一个或多个系统组件。

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