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1. 发明申请

WO2017063956A1 LOGIC BLOCK ARCHITECTURE FOR PROGRAMMABLE GATE ARRAY 审中-公开
标题翻译：用于可编程栅阵列的逻辑块结构
公开(公告)号：WO2017063956A1
公开(公告)日：2017-04-20
申请号：PCT/EP2016/074075
申请日：2016-10-07
申请人： MENTA
发明人： ROUGE, Laurent , EYDOUX, Julien , MARTHELY, Serge Alexandre
IPC分类号： H03K19/177
CPC分类号： H03K19/17776 , H03K19/17728
摘要： A programmable logic block for a FPGA comprises two Lookup Tables (LUT) (41, 44). The configuration information for these LUTs (41, 44) is provided by a programmable controller (43), which itself incorporates LUT functionality. This intermediate layer of LUT functionality provides a means to programmatically control the behaviour of the primary LUTs (41, 44) in an operational mode, on the basis of settings made during an initialization mode. Certain embodiments also incorporate a Logic circuit (35), which together with the programmable behaviour of the Primary LUTs provides a means for efficiently implementing a number of common logic functions in including adders, multiplexers, parity and extended LUT and Multiplexer functions. A method for programming an FPGA comprising such a programmable logic block and corresponding data stream are also described.
摘要翻译：用于FPGA的可编程逻辑块包括两个查找表（LUT）（41,44）。这些LUT（41,44）的配置信息由可编程控制器（43）提供，该可编程控制器本身结合了LUT功能。 LUT功能的这个中间层提供了一种手段，用于在初始化模式期间基于设置来以编程方式控制操作模式中的主LUT（41,44）的行为。某些实施例还包括逻辑电路（35），其连同主LUT的可编程行为一起提供用于在包括加法器，多路复用器，奇偶校验和扩展LUT和多路复用器功能的情况下有效实施多个公共逻辑功能的手段。还描述了用于编程包括这种可编程逻辑块和相应数据流的FPGA的方法。

2. 发明申请

WO2017063957A1 SYSTEM AND METHOD FOR TESTING AND CONFIGURATION OF AN FPGA 审中-公开
标题翻译：用于测试和配置FPGA的系统和方法
公开(公告)号：WO2017063957A1
公开(公告)日：2017-04-20
申请号：PCT/EP2016/074076
申请日：2016-10-07
申请人： MENTA
发明人： ROUGE, Laurent , EYDOUX, Julien , GIUFFRE, Marcello
IPC分类号： H03K19/177 , G01R31/28
CPC分类号： H03K19/17728 , G01R31/28 , H03K19/17764
摘要： Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.
摘要翻译：在FPGA中的查找表（LUT）和可编程路由开关的配置值通过安排在移位寄存器中的许多触发器来提供。该移位寄存器可以在工厂测试模式下接收测试值，并且可以在操作模式下接收操作配置值（实现客户需要的FPGA的任何功能）。比特流在移位寄存器的一端提供，并直到最后一个触发器收到其值。也可以在移位寄存器的另一端输出数值以与初始比特流进行比较，以便识别存储值的损坏，例如，由于辐射暴露。提出了一种时钟门控架构，用于将数据加载到特定选定的移位寄存器或从特定选定的移位寄存器读取数据

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