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    • 8. 发明申请
    • FINE-GRAIN DYNAMICALLY RECONFIGURABLE FPGA ARCHITECTURE
    • 精细动态可重构FPGA架构
    • WO2014123616A1
    • 2014-08-14
    • PCT/US2013/073131
    • 2013-12-04
    • THE TRUSTEES OF PRINCETON UNIVERSITYLIN, Ting-JungZHANG, WeiJHA, Niraj K.
    • LIN, Ting-JungZHANG, WeiJHA, Niraj K.
    • H03K19/173
    • H03K19/1776H03K19/0008H03K19/17728H03K19/17736H03K19/17752
    • A field programmable gate array (FPGA) and method of reconfiguring a FPGA are disclosed. The FPGA includes a plurality of logic elements interconnected with reconfigurable switches and at least horizontal and vertical direct links. A memory is coupled to the reconfigurable switches, the memory being configured to store at least two run time configurations. The reconfigurable switches are reconfigurable based on a selected run time configuration stored in the memory. The memory may be a nanoelectronic random access memory (RAM). The memory may be configured to store the at least two run time configurations for at least four logic elements. Each logic element may include a look-up-table (LUT), a flip-flop, inputs and outputs. Each logic element may include dedicated carry logic. At least four logic elements may be interconnected with diagonal direct links.
    • 公开了一种现场可编程门阵列(FPGA)及其配置方法。 FPGA包括与可重新配置的交换机和至少水平和垂直的直接链路互连的多个逻辑元件。 存储器耦合到可重新配置的交换机,该存储器被配置为存储至少两个运行时配置。 基于存储在存储器中的所选择的运行时间配置,可重新配置的交换机是可重新配置的。 存储器可以是纳米电子随机存取存储器(RAM)。 存储器可以被配置为存储用于至少四个逻辑元件的至少两个运行时配置。 每个逻辑元件可以包括查找表(LUT),触发器,输入和输出。 每个逻辑元件可以包括专用进位逻辑。 至少四个逻辑元件可以与对角线直接链路互连。