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1. 发明申请

WO1997024726A1 METHOD AND APPARATUS FOR A LOW POWER SELF-TIMED MEMORY CONTROL SYSTEM 审中-公开
标题翻译：一种低功耗自记忆控制系统的方法与装置
公开(公告)号：WO1997024726A1
公开(公告)日：1997-07-10
申请号：PCT/US1996020259
申请日：1996-12-06
申请人： LSI LOGIC CORPORATION
发明人： LSI LOGIC CORPORATION , PASSOW, Robin, W. , PRIEBE, Gordon, W. , ISLIEFSON, Ronald, D. , MACTAGGART, I., Ross , LECLAIR, Kevin, R.
IPC分类号： G11C07/00
CPC分类号： G11C7/08 , G11C7/14 , G11C7/22 , G11C7/227
摘要： A self-timed memory control system including a dummy row and column of memory cells along adjacent edges of a core memory array. Control logic receives an external clock signal and initiates address decoding, and also asserts a sense enable signal for activating the sense amplifiers. A dummy driver receives the enable signal and asserts a select signal on a dummy select line, which causes a memory access to occur in the dummy portion simultaneously with each access of the core memory array. A fixed memory cell in the dummy path always asserts a logic zero to a dummy sense amplifier, which senses the logic zero and respondingly asserts a timing signal. The dummy sense amplifier is biased with a voltage offset to favor a logic one, so that the timing signal is preferably delayed until after the output data of the core memory array has stabilized. The control logic detects the assertion of the timing signal and respondingly latches the output data, and the control logic also shuts down the sense amplifiers to prevent further power drain. In this manner, the output data is latched and the sense amplifiers are disabled as soon as possible to conserve energy but within a safe timing margin to assure that valid data is properly latched. A biased inverter is preferably added for further timing margin. The sense amplifiers preferably include an input level-shifter stage for proper operation at low voltage levels.
摘要翻译：一种自定时存储器控制系统，包括沿核心存储器阵列的相邻边缘的虚拟行和存储单元列。控制逻辑接收外部时钟信号并启动地址解码，并且还断言用于激活读出放大器的检测使能信号。虚拟驱动器接收使能信号并且在虚拟选择线路上断言选择信号，这导致在核心存储器阵列的每次访问的同时在虚拟部分中发生存储器访问。虚拟路径中的固定存储单元总是向虚拟读出放大器置位逻辑0，该虚拟读出放大器检测逻辑零并且响应地断言定时信号。虚拟读出放大器被电压偏置偏置以有利于逻辑读出放大器，使得定时信号优选地被延迟直到核心存储器阵列的输出数据已经稳定为止。控制逻辑检测到定时信号的断言，并且响应地锁存输出数据，并且控制逻辑还关闭读出放大器以防止进一步的功率消耗。以这种方式，输出数据被锁存，并且读出放大器尽快被禁用以节省能量，但是在安全的时序余量内，以确保有效的数据被正确锁存。优选地增加偏置的反相器用于进一步的定时裕度。感测放大器优选地包括用于在低电压电平下正常工作的输入电平移位器级。

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