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1. 发明申请

WO2003067478A1 VERIFICATION OF EMBEDDED TEST STRUCTURES IN CIRCUIT DESIGNS 审中-公开
标题翻译：电路设计中嵌入式测试结构的验证
公开(公告)号：WO2003067478A1
公开(公告)日：2003-08-14
申请号：PCT/US2003/001830
申请日：2003-01-23
申请人： LOGICVISION, INC. , PRICE, Paul , CÔTÉ, Jean-François , VERMA, Ajit, Kumar
发明人： PRICE, Paul , CÔTÉ, Jean-François , VERMA, Ajit, Kumar
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G01R31/31704 , G01R31/318342 , G01R31/318536 , G06F17/5045
摘要： An embedded test structure verification tool (100) for use in generating test benches for verifying test structures embedded in a circuit, comprises a verification specification processor (102) for parsing a verification specification (106) containing test specifications for selected test structures and a test bench generator (104) for each of one or more types of embedded test structures, each test bench generator being operable to process a test structure specification of a test structure of a corresponding test structure type and generate a test bench (108) using data contained in said test specifications of said verification specification, data contained in said test structure specification and data contained in a test connection specification.
摘要翻译：一种嵌入式测试结构验证工具（100），用于生成用于验证嵌入电路中的测试结构的测试台，包括用于解析包含所选测试结构的测试规范的验证规范（106）的验证规范处理器（102）每个测试台发生器可操作以处理相应测试结构类型的测试结构的测试结构规范，并使用包含的测试结构类型的数据生成测试台（108）在所述验证规范的所述测试规范中，包含在所述测试结构规范中的数据和包含在测试连接规范中的数据。

2. 发明申请

WO2003065147A3 METHOD AND PROGRAM PRODUCT FOR CREATING AND MAINTAINING SELF-CONTAINED DESIGN ENVIRONMENT 审中-公开
公开(公告)号：WO2003065147A3
公开(公告)日：2003-08-07
申请号：PCT/US2003/001831
申请日：2003-01-23
申请人： LOGICVISION, INC. , PAJAK, Brian, John , PRICE, Paul , CÔTÉ, Jean-François , ROMAIN, Luc
发明人： PAJAK, Brian, John , PRICE, Paul , CÔTÉ, Jean-François , ROMAIN, Luc
IPC分类号： G01R31/14
摘要： An embedded test, chip design utility is an ease-of-use utility for assisting a circuit designer in quickly implementing a circuit embedded test design flow (70). Using the utility, a designer transforms a design netlist to include embedded test structures. The utility automatically builds a workspace containing a predetermined repository structure and design environment (212), generates control files (214) for executing design automation tools that operate within the design flow, and encapsulates the data so as to be self-contained and easily transferable to other design teams.

3. 发明申请

WO2003067477A1 METHOD AND PROGRAM PRODUCT FOR COMPLETING A CIRCUIT DESIGN HAVING EMBEDDED TEST STRUCTURES 审中-公开
标题翻译：用于完成具有嵌入式测试结构的电路设计的方法和程序产品
公开(公告)号：WO2003067477A1
公开(公告)日：2003-08-14
申请号：PCT/US2003/001829
申请日：2003-01-23
申请人： LOGICVISION, INC. , CÔTÉ, Jean-François , PRICE, Paul
发明人： CÔTÉ, Jean-François , PRICE, Paul
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G01R31/31704 , G01R31/318342 , G01R31/318536 , G06F17/5045
摘要： A sign-off method for use in verifying of embedded test structures in a circuit design extracts a description of all embedded test structures from a circuit description to create a test connection map file (52), and verifies the connections of the test structures to circuit pins or nets, creates verification configuration files for use in performing a sign-off verification of the circuit, for a circuit containing logic test structures (56), verifies that each logic test structure complies with logic test design rules and creates logic test vectors and a reference signature (58), performs a formal verification (60) and a static timing analysis of the circuit (62), generates a sign-off simulation test bench for each test structure using the verification configuration files and the test connection map file, executes the test benches to simulate all test structures in the circuit (66); and creates manufacturing test patterns (80).
摘要翻译：用于验证电路设计中嵌入式测试结构的签名方法从电路描述中提取所有嵌入式测试结构的描述，以创建测试连接映射文件（52），并验证测试结构与电路的连接引脚或网络创建用于执行电路的签发验证的验证配置文件，对于包含逻辑测试结构（56）的电路，验证每个逻辑测试结构符合逻辑测试设计规则并创建逻辑测试向量，并且参考签名（58）执行电路（62）的形式验证（60）和静态定时分析，使用验证配置文件和测试连接映射文件为每个测试结构生成签发模拟测试台，执行测试台以模拟电路中的所有测试结构（66）; 并创建制造测试图案（80）。

4. 发明申请

WO2004003967A2 SCAN TEST METHOD PROVIDING REAL TIME IDENTIFICATION OF FAILING TEST PATTERNS AND TEST CONTROLLER FOR USE THEREWITH 审中-公开
标题翻译：提供故障测试模式的实时识别的扫描测试方法及其使用的测试控制器
公开(公告)号：WO2004003967A2
公开(公告)日：2004-01-08
申请号：PCT/US2003/015434
申请日：2003-05-16
申请人： LOGICVISION, INC. , CÔTÉ, Jean-François , NADEAU-DOSTIE, Benoit
发明人： CÔTÉ, Jean-François , NADEAU-DOSTIE, Benoit
IPC分类号： H01L
CPC分类号： G01R31/318563 , G01R31/318555 , G01R31/318566 , G06F2201/83
摘要： A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register; replacing the test response signature in the signature register with a test block expected signature; identifying the block as a failing test block when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.
摘要翻译：一种对集成电路进行扫描测试以提供具有至少一个故障测试模式的测试模式块的实时识别的方法包括执行多个测试操作并将对应于每个测试模式块的测试响应签名存储到签名寄存器 ; 用测试块预期签名代替签名寄存器中的测试响应签名; 当测试响应签名与测试块预期签名不同时，将块识别为失败的测试块; 并重复前面的步骤，直到测试完成。

5. 发明申请

WO2003067386A3 METHOD AND SYSTEM FOR LICENSING INTELLECTUAL PROPERTY CIRCUITS 审中-公开
公开(公告)号：WO2003067386A3
公开(公告)日：2003-08-14
申请号：PCT/US2003/003421
申请日：2003-02-04
申请人： LOGICVISION, INC. , HOWELLS, Michael, C. , CÔTÉ, Jean-François
发明人： HOWELLS, Michael, C. , CÔTÉ, Jean-François
IPC分类号： G06F17/60
摘要： A method of controlling access to Intellectual Property (IP) blocks (42) embedded in a circuit comprises a decoding a circuit usage rights file (56) associated with the circuit and delineating usage rights associated with the IP blocks, determining from the circuit usage rights file (56) whether access to an IP block (42) to be accessed is permitted; and accessing the IP block only if access in permitted.

6. 发明申请

WO2003102964A1 METHOD FOR COLLECTING FAILURE INFORMATION FOR A MEMORY USING EMBEDDED TEST CONTROLLER 审中-公开
标题翻译：收集使用嵌入式测试控制器的存储器的故障信息的方法
公开(公告)号：WO2003102964A1
公开(公告)日：2003-12-11
申请号：PCT/US2003/013721
申请日：2003-05-02
申请人： LOGICVISION, INC. , NADEAU-DOSTIE, Benoit , CÔTÉ, Jean-François
发明人： NADEAU-DOSTIE, Benoit , CÔTÉ, Jean-François
IPC分类号： G11C29/00
CPC分类号： G11C29/44
摘要： A method of collecting failure information when testing a memory comprises: performing a test of the memory according to a test algorithm, and, while performing the test, counting failure events (114) which occur after a predetermined number of masked events (106); stopping the test upon occurrence of a stopping criterion (112) which comprises one of occurrence of a first failure event (110), a change of a test operation; a change of a memory column address; a change of a memory row address; a change of a memory bank address; and a change of a test algorithm phase; and storing failure information.
摘要翻译：在测试存储器时收集故障信息的方法包括：根据测试算法对存储器进行测试，并且在执行测试的同时，在预定数量的屏蔽事件（106）之后发生的计数故障事件（114）; 在出现停止标准（112）时停止测试，该停止标准包括第一故障事件（110）的发生，测试操作的改变; 更改内存列地址; 更改内存行地址; 更改存储库地址; 并改变测试算法阶段; 并存储故障信息。

7. 发明申请

WO2003067760A1 METHOD AND CIRCUITRY FOR CONTROLLING CLOCKS OF EMBEDDED BLOCKS DURING LOGIC BIST TEST MODE 审中-公开
标题翻译：在逻辑测试模式下控制嵌入式块的时钟的方法和电路
公开(公告)号：WO2003067760A1
公开(公告)日：2003-08-14
申请号：PCT/US2003/003140
申请日：2003-02-03
申请人： LOGICVISION, INC. , NADEAU-DOSTIE, Benoit , CÔTÉ, Jean-François
发明人： NADEAU-DOSTIE, Benoit , CÔTÉ, Jean-François
IPC分类号： H03K19/00
CPC分类号： G01R31/3187
摘要： A method of designing an integrated circuit for distributing test clock signals to embedded cores (FIG. 2) having at least one core functional clock input comprises, for each core, providing a clock gating circuit (46) for selectively disabling a core functional clock signal applied to a core primary clock input; and providing a core clock selection circuit (50) for each secondary core functional clock input for selecting one of a core functional clock signal output by the gating circuit and a core test clock signal and applying a selected signal to the each secondary core functional clock input.
摘要翻译：设计用于将测试时钟信号分配给具有至少一个核心功能时钟输入的嵌入式核心（图2）的集成电路的方法包括：为每个核心提供时钟选通电路（46），用于选择性地禁用核心功能时钟信号应用于核心主时钟输入; 以及提供用于每个次级核心功能时钟输入的核心时钟选择电路（50），用于选择由门控电路输出的核心功能时钟信号和核心测试时钟信号之一，并将所选择的信号施加到每个次级核心功能时钟输入。

8. 发明申请

WO2003038450A2 METHOD AND PROGRAM PRODUCT FOR DESIGNING HIERARCHICAL CIRCUIT FOR QUIESCENT CURRENT TESTING 审中-公开
标题翻译：用于设计电流电流测试的分层电路的方法和程序产品
公开(公告)号：WO2003038450A2
公开(公告)日：2003-05-08
申请号：PCT/CA2002/001582
申请日：2002-10-22
申请人： LOGICVISION, INC. , NADEAU-DOSTIE, Benoit , CÔTÉ, Jean-François
发明人： NADEAU-DOSTIE, Benoit , CÔTÉ, Jean-François
IPC分类号： G01R
CPC分类号： G01R31/3012
摘要： A method of designing integrated circuits having an hierarchical structure for quiescent current testing comprises analyzing each of one or more selected hierarchical blocks independently of other selected blocks to identify any circuit states of each block which could result in elevated quiescent current levels during quiescent current testing of the circuit, the analysis beginning with blocks at a lowest level of hierarchy and proceeding in sequence through each level of design hierarchy to a highest level of hierarchy containing a top-level block; and calculating a fault coverage for each selected block.
摘要翻译：设计具有用于静态电流测试的层级结构的集成电路的方法包括独立于其它所选择的块来分析一个或多个选择的分层块中的每一个，以识别每个块的任何电路状态，这可能导致在静态电流测试期间提高的静态电流水平电路，分析以最低层次结构的块开始，并通过每个级别的设计层次顺序进行到包含顶级块的最高层级; 并计算每个所选块的故障覆盖。

9. 发明申请

WO2002088945A1 METHOD OF DESIGNING CIRCUIT HAVING MULTIPLE TEST ACCESS PORTS, CIRCUIT PRODUCED THEREBY AND METHOD OF USING SAME 审中-公开
标题翻译：设计具有多个测试访问端口的电路的方法，其生产的电路及其使用方法
公开(公告)号：WO2002088945A1
公开(公告)日：2002-11-07
申请号：PCT/US2002/012267
申请日：2002-04-19
申请人： LOGICVISION, INC. , NADEAU-DOSTIE, Benoit , CÔTÉ, Jean-François
发明人： NADEAU-DOSTIE, Benoit , CÔTÉ, Jean-François
IPC分类号： G06F9/455
CPC分类号： G01R31/318563 , G01R31/318555
摘要： In a circuit with multiple Test Access Port (TAP) interfaces, the TAPs are arranged into groups, with secondary TAPs in one or more groups (22) and a master TAP (12) in another group (24), the master TAP (12) having an instruction register with bits for storing a group selection code; a Test Data Output (TDO) circuit responsive to the group selection code connects the group TDO of one of the groups to the circuit TDO; and, for each secondary TAP group (22), a group Test Data Input (TDI) circuit responsive to a shift state signal for selectively connecting the group TDI to the circuit TDI or to the output of a padding register having its input connected to the circuit TDI, and its output connected to an input of the group TDI circuit; and a group TMS circuit responsive to a predetermined TAP selection code associated with the group for producing a group TMS signal for each TAP in the group.
摘要翻译：在具有多个测试访问端口（TAP）接口的电路中，TAP被分组，其中一个或多个组（22）中的辅助TAP和另一个组（24）中的主TAP（12），主TAP（12））具有用于存储组选择代码的位的指令寄存器; 响应于组选择代码的测试数据输出（TDO）电路将组中的一组的组TDO连接到电路TDO; 并且对于每个辅助TAP组（22），响应于移位状态信号的组测试数据输入（TDI）电路，用于选择性地将组TDI连接到电路TDI或将其输入连接到电路TDI的填充寄存器的输出电路TDI，其输出连接到组TDI电路的输入; 以及响应于与该组相关联的预定TAP选择码的组TMS电路，用于为该组中的每个TAP产生组TMS信号。

10. 发明申请

WO2002063313A2 METHOD FOR SCAN TESTING OF DIGITAL CIRCUIT, DIGITAL CIRCUIT AND PROGRAM PRODUCT 审中-公开
标题翻译：数字电路，数字电路和程序产品扫描测试方法
公开(公告)号：WO2002063313A2
公开(公告)日：2002-08-15
申请号：PCT/US2002/001586
申请日：2002-01-22
申请人： LOGICVISION, INC. , NADEAU-DOSTIE, Benoit , CÔTÉ, Jean-François
发明人： NADEAU-DOSTIE, Benoit , CÔTÉ, Jean-François
IPC分类号： G01R
CPC分类号： G01R31/318552 , G01R31/318563
摘要： A method for at-speed scan testing of circuits having scannable memory elements which source multi-cycle paths having propagation delays that are longer than the period of a system clock used during normal operation comprises loading a test stimulus into the memory elements; performing a capture operation, including configuring in capture mode throughout the capture operation, non-source elements and multi-cycle path source elements which have a predetermined maximum capture clock rate which is the same as or higher than the capture clock rate; and configuring in a hold mode during all but the last cycle of the capture operation and in capture mode for the last cycle, source elements which have a predetermined maximum capture clock rate which is lower than the capture clock rate; applying at least two clock cycles of the capture clock; and unloading test response data captured by the memory elements.
摘要翻译：一种用于对具有可扫描存储器元件的电路进行高速扫描测试的方法，所述可扫描存储器元件源于具有比在正常操作期间使用的系统时钟的周期长的传播延迟的多周期路径包括将测试激励加载到存储器元件中; 执行捕获操作，包括在整个捕获操作期间以捕获模式配置非源元件和多周期路径源元件，其具有与捕获时钟速率相同或更高的预定最大捕获时钟速率; 以及在捕捉操作的最后周期以及在最后周期的捕获模式期间的所有除了最后周期之内的所有保持模式下进行配置，所述源元件具有低于所述捕获时钟速率的预定最大捕获时钟速率; 应用捕获时钟的至少两个时钟周期; 并卸载由存储器元件捕获的测试响应数据。

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