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1. 发明申请

WO2020049176A1 METHOD OF FABRICATION OF AN INTEGRATED SPIRAL INDUCTOR HAVING LOW SUBSTRATE LOSS 审中-公开
公开(公告)号：WO2020049176A1
公开(公告)日：2020-03-12
申请号：PCT/EP2019/073898
申请日：2019-09-06
申请人： LFOUNDRY S.R.L
发明人： SCHMIDT, Carsten , SPITZLSPERGER, Gerhard
IPC分类号： H01L23/522 , H01L21/84 , H01L27/13
摘要： After finishing of the front side CMOS manufacturing process, the silicon wafer is permanently bonded with its front side onto a carrier wafer. The carrier wafer is a high resistivity silicon wafer or a wafer of a dielectric or of a ceramic material. The silicon substrate of the device wafer is thinned from the back side such that the remaining silicon0thickness is only a few micrometers. In the area dedicated to a spiral inductor, the substrate material is entirely removed by a masked etching process and the resulting gap is filled with a dielectric material. A spiral inductor coil is formed on the backside of the wafer on top of the dielectric material. The inductor coil is connected to the CMOS circuits on the front side by through-silicon vias.

2. 发明申请

WO2020104998A1 HALL INTEGRATED CIRCUIT AND CORRESPONDING METHOD OF MANUFACTURING OF A HALL INTEGRATED CIRCUIT USING WAFER STACKING 审中-公开
公开(公告)号：WO2020104998A1
公开(公告)日：2020-05-28
申请号：PCT/IB2019/060044
申请日：2019-11-21
申请人： LFOUNDRY S.R.L.
发明人： SCHMIDT, Carsten , BLASINI, Mario , SPITZLSPERGER, Gerhard , MONTAGNA, Alessandro
IPC分类号： H01L43/14 , H01L27/22 , H01L43/06
摘要： A Hall integrated circuit including a vertical Hall element (100), having a first wafer (10) and a second wafer (20) stacked in a vertical direction (z), the second wafer (20) including a CMOS substrate (201) integrating a CMOS processing circuit coupled to the vertical Hall element (100) and a stack (204) of dielectric layers arranged on the CMOS substrate (201), and the first wafer (10) including a Hall-sensor layer (102) having a first surface (10b) and a second surface (10d) opposed along the vertical direction (z) and extending in a horizontal plane (xy), orthogonal to the vertical direction (z), the first and second wafers (10, 20) being bonded with the interposition of a dielectric layer (105) arranged above the first surface (10b) of the Hall-sensor layer (102). The vertical Hall element (100) has: at least a first Hall terminal (1), being a first doped region arranged at the first surface (10b) of the Hall-sensor layer (102); at least a second Hall terminal (4), being a second doped region arranged at the second surface (10d) of the Hall-sensor layer (102) aligned to the first doped region along the vertical direction (z) and separated therefrom by the thickness of the Hall-sensor layer (102); a deep trench isolation ring (107) extending through the Hall-sensor layer (102) from the first surface (10b) to the second surface (10d) and enclosing and isolating a Hall sensor region of the Hall-sensor layer (102), wherein the first and second Hall terminals (1, 4) are arranged; and a first and a second conductive structures (111, 114) coupled to the first, respectively, the second Hall terminal (1, 4) and electrically connected to respective contact pads (221, 224) embedded in the stack (204) of the second wafer (20).

3. 发明申请

WO2015128479A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PRODUCT 审中-公开
标题翻译：制造半导体器件和半导体产品的方法
公开(公告)号：WO2015128479A1
公开(公告)日：2015-09-03
申请号：PCT/EP2015/054170
申请日：2015-02-27
申请人： LFOUNDRY S.R.L.
发明人： SPITZLSPERGER, Gerhard , SCHMIDT, Carsten
IPC分类号： H01L21/768 , H01L21/74 , H01L21/762 , H01L29/66 , H01L29/417 , H01L29/78 , H01L21/8234
CPC分类号： H01L23/562 , H01L21/743 , H01L21/76224 , H01L21/76898 , H01L21/823418 , H01L23/5226 , H01L23/528 , H01L24/43 , H01L27/092 , H01L29/0634 , H01L29/0649 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41708 , H01L29/4175 , H01L29/41766 , H01L29/66272 , H01L29/66333 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66712 , H01L29/732 , H01L29/7395 , H01L29/7398 , H01L29/74 , H01L29/7802 , H01L29/7811 , H01L29/7823 , H01L29/7824 , H01L29/7835 , H01L29/808 , H01L2224/4502
摘要： A method of fabricating a semiconductor product includes the processing of a semiconductor wafer(10)from a front surface including structures disposed in the substrate (100) of the wafer adjacent to the front surface and the forming of at least one wiring (110) embedded in a dielectric layer (111) disposed on the front surface of the wafer. The semiconductor wafer is mounted to a carrier wafer (120) at its front surface so that material can be removed from the backside of the wafer to thin the semiconductor wafer. Backside processing of the semiconductor wafer includes the forming of implantations from the backside of the wafer, the forming of deep trenches (132a, 132b) to isolate the structures from other structures within the wafer, the forming of a through silicon via (134) to contact features on the front side of the wafer and the forming of a body contact (131). Several devices can be generated within the same wafer.
摘要翻译：一种制造半导体产品的方法包括从前表面处理半导体晶片（10），所述前表面包括设置在所述晶片的与所述前表面相邻的所述基板（100）中的结构，以及形成嵌入的至少一个布线（110）在设置在晶片的前表面上的电介质层（111）中。半导体晶片在其前表面安装到载体晶片（120），使得可以从晶片的背面去除材料以使半导体晶片变薄。半导体晶片的背面处理包括从晶片的背面形成注入，形成深沟槽（132a，132b）以将结构与晶片内的其它结构隔离，通过硅（134）形成至晶片前侧的接触特征以及身体接触（131）的形成。可以在同一晶片内产生多个器件。

4. 发明申请

WO2021005532A1 HALL INTEGRATED SENSOR AND CORRESPONDING MANUFACTURING PROCESS 审中-公开
公开(公告)号：WO2021005532A1
公开(公告)日：2021-01-14
申请号：PCT/IB2020/056427
申请日：2020-07-08
申请人： LFOUNDRY S.R.L.
发明人： SCHMIDT, Carsten , SPITZLSPERGER, Gerhard , HOHNLOSER, Daniel
IPC分类号： G01R33/00 , G01R33/07
摘要： An integrated Hall sensor is provided with: a main wafer (10) of semiconductor material having a substrate (101) with a first surface (101a) and a second surface (101b), opposite to the first surface (101a) along a vertical axis (y); Hall sensor terminals (1, 2, 3, 4; 1', 2', 3', 4') arranged at at least one of the first and second surfaces (101a, 101b) of the substrate (101); an isolation structure (109) in the substrate (101) defining a Hall sensor plate (103) of the integrated Hall sensor, the Hall sensor terminals being arranged in the isolation structure (109). The integrated Hall sensor moreover has a test or calibration coil integrated in the wafer (10), having a plurality of windings formed, at least in part, by metal portions (130b, 170b; 130a, 170a) arranged above the first and second surfaces (101a, 101b) of the substrate (101) and defining an inner volume (1001) entirely enclosing the Hall sensor plate (103).

5. 发明申请

WO2020058473A1 SEMICONDUCTOR VERTICAL SCHOTTKY DIODE AND METHOD OF MANUFACTURING THEREOF 审中-公开
公开(公告)号：WO2020058473A1
公开(公告)日：2020-03-26
申请号：PCT/EP2019/075320
申请日：2019-09-20
申请人： LFOUNDRY S.R.L.
发明人： SCHMIDT, Carsten , SPITZLSPERGER, Gerhard
IPC分类号： H01L29/872 , H01L27/06 , H01L21/329 , H01L29/417 , H01L29/06
摘要： A semiconductor vertical Schottky diode device (300; 400; 500; 600; 700), having: a substrate (101) of semiconductor material, with a front surface (101a) and a back surface (101b'); a lightly doped region (102) formed in a surface portion of the substrate (101) facing the front surface (101a), having a first conductivity type; a first electrode (111) formed on the lightly doped region (102) on the front surface (101a) of the substrate (101), to establish a Schottky contact; a highly doped region (140) at the back surface (101b') of the substrate (101), in contact with the lightly doped region (102) and having the first conductivity type; and a second electrode (160a) electrically in contact with the highly doped region (140), on the back surface (101b') of the substrate (101), to establish an Ohmic contact.

6. 发明申请

WO2019219941A1 VERTICAL HALL ELEMENTS HAVING REDUCED OFFSET AND METHOD OF MANUFACTURING THEREOF 审中-公开
公开(公告)号：WO2019219941A1
公开(公告)日：2019-11-21
申请号：PCT/EP2019/062866
申请日：2019-05-17
申请人： LFOUNDRY S.R.L.
发明人： SCHMIDT, Carsten , SPITZLSPERGER, Gerhard
IPC分类号： H01L43/06 , H01L43/14 , H01L27/22
摘要： Vertical Hall elements are disclosed which comprise a substrate (101) of a first conductivity type having a first surface (101a) and a second surface (101b), a well (102) of a second conductivity type disposed in and exposed on both surfaces of the substrate, and at least four terminals, preferably comprising highly doped regions of the second conductivity type, in contact with the well. At least two terminals (1, 2) are arranged on the first surface, and at least two terminals (3, 4) are arranged on the second surface such that one terminal (1) on the first surface and one terminal (4) on the second surface have the same but opposite location in a cross-section orthogonal to the substrate surfaces. Alternatively, an element comprises one central pair of opposite surface terminals, whereas the other two terminals comprise lateral buried doped regions (151a, 151c) connecting to the first surface.

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