专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2005027339A1 MIXER CIRCUIT, RECEIVER COMPRISING A MIXER CIRCUIT, METHOD FOR GENERATING AN OUTPUT SIGNAL BY MIXING AN INPUT SIGNAL WITH AN OSCILLATOR SIGNAL 审中-公开
标题翻译：混合电路，包含混频器电路的接收器，通过混合输入信号与振荡器信号产生输出信号的方法
公开(公告)号：WO2005027339A1
公开(公告)日：2005-03-24
申请号：PCT/IB2004/051615
申请日：2004-08-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V., , BREEMS, Lucien, J. , SANDIFORT, Quino, A. , SCHUURMANS, Han, M.
发明人： BREEMS, Lucien, J. , SANDIFORT, Quino, A. , SCHUURMANS, Han, M.
IPC分类号： H03D7/14
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1491 , H03D2200/0025
摘要： The invention relates to a mixer circuit, a receiver comprising a mixer circuit, and a method of mixing an input signal with an oscillator signal. A mixer circuit 300 according to the invention comprises a first input node 301 and a second input node 302 for receiving an input signal Vin, a first output node 321 and a second output node 322, voltage to-current conversion means Rla, Rlb, R2a, R2b, and switching means M1, M2, M3, M4 operatively coupled to each other and to the first input node 301, the second input node 302, the first output node 321, and the second output node 322 to generate a mixed input signal at the first output node 321 and the second output node 322 in response to an oscillator signal. The voltage-to-current conversion means Rla, Rlb, R2a, R2b comprises a first voltage-to current converter RI a, R2a for generating a first current at a first switching node 311 and a third current at a third switching node 313 in response to the input signal Vin, and a second voltage-to-current converter Rlb, R2b for generating a second current at a second switching node 312 and a fourth current a fourth switching node 314 in response to the input signal Vin. The switching means M1, M2, M3, M4 is arranged to couple the second switching node 312 to the second output node 322 and the third switching node 313 to the first output node 321 during a first phase ϕ1 of the oscillator signal; and the first switching node 311 to the first output node 321 and the fourth switching node 314 to the second output node 322 during a second phase ϕ2 of the oscillator signal. As a result first and third switching nodes 311, 313 are isolated from respectively second and fourth switching node 312, 314. This prevents cross-over distortion from parasitic capacitances associated with first and third switching nodes 311, 313 via respective switches M2 and M4, and vice versa from parasitic capacitances associated with second and fourth switching nodes 312, 314 via respective switches M1 and M3.
摘要翻译：本发明涉及混频器电路，包括混频器电路的接收机以及混合输入信号与振荡器信号的方法。根据本发明的混频器电路300包括用于接收输入信号Vin的第一输入节点301和第二输入节点302，第一输出节点321和第二输出节点322，电压到电流转换装置R 1a，R 1b，R 2a ，R2b以及可操作地耦合到第一输入节点301，第二输入节点302，第一输出节点321和第二输出节点322的开关装置M1，M2，M3，M4，以产生混合输入信号在第一输出节点321和第二输出节点322响应于振荡器信号。电压 - 电流转换装置Rla，Rlb，R2a，R2b包括用于在第一开关节点311产生第一电流的第一电压 - 电流转换器RIa和响应于第三开关节点313的第三电流以及用于响应于输入信号Vin在第二开关节点312产生第二电流的第二电压 - 电流转换器R1b和第二电流转换器R1b，以及第四电流和第四开关节点314。开关装置M1，M2，M3，M4布置成在振荡器信号的第一相位φ1期间将第二开关节点312耦合到第二输出节点322和第三开关节点313到第一输出节点321; 以及在振荡器信号的第二相位φ2期间，第一切换节点311到第一输出节点321和第四切换节点314到第二输出节点322。结果，第一和第三开关节点311,313分别与第二和第四开关节点312,314分离。这防止了经由相应开关M2和M4的与第一和第三开关节点311,313相关联的寄生电容的交叉失真，反之亦然，通过相应的开关M1和M3与第二和第四开关节点312,314相关联的寄生电容。

2. 发明申请

WO2005027351A1 METHOD FOR CALIBRATING A MULTI-BIT DIGITAL-TO-ANALOG CONVERTER, MULTI-BIT DIGITAL-TO-ANALOG CONVERTER IN WHICH THIS METHOD IS APPLIED AND CONVERTER PROVIDED WITH SUCH A MULTI-BIT DIGITAL-TO-ANALOG CONVERTER 审中-公开
标题翻译：用于校准多位数字到模拟转换器的方法，该方法应用的多位数字到模拟转换器和具有这种多位数字到模拟转换器的转换器
公开(公告)号：WO2005027351A1
公开(公告)日：2005-03-24
申请号：PCT/IB2004/051744
申请日：2004-09-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BREEMS, Lucien, J. , BAJDECHI, Ovidiu
发明人： BREEMS, Lucien, J. , BAJDECHI, Ovidiu
IPC分类号： H03M1/10
CPC分类号： H03M1/1004
摘要： In a method for calibrating a multi-bit DAC intended, particularly, for application in high-speed and high-resolution ADCs, such as Σ Δ ADCs, and comprising a number of DAC cells, apart from the number of DAC cells applied in the multi-bit DAC for conversion, an additional DAC cell is provided, which can be interchanged with each of the other DAC cells in order to switch each DAC cell successively from the multi-bit DAC into a calibration circuit to calibrate said DAC cell without interrupting the conversion. The calibration circuit includes means for measuring errors in the DAC cell under calibration and means for correcting said DAC cell.
摘要翻译：在用于校准多位DAC的方法中，特别是用于在高速和高分辨率ADC（例如Sigma Delta ADC）中应用并且包括多个DAC单元的方法，除了在用于转换的多位DAC，提供了另外的DAC单元，其可以与每个其它DAC单元互换，以便将每个DAC单元从多位DAC连续切换到校准电路，以校准所述DAC单元而不中断转换。校准电路包括用于测量校准期间DAC单元中的误差的装置以及用于校正所述DAC单元的装置。

3. 发明申请

WO2007113735A1 CALIBRATION CIRCUIT AND METHOD FOR A/D CONVERTER 审中-公开
标题翻译：校准电路和A / D转换器的方法
公开(公告)号：WO2007113735A1
公开(公告)日：2007-10-11
申请号：PCT/IB2007/051072
申请日：2007-03-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BREEMS, Lucien, J. , RUTTEN, Robert , VAN DER PLOEG, Hendrik
发明人： BREEMS, Lucien, J. , RUTTEN, Robert , VAN DER PLOEG, Hendrik
IPC分类号： H03M1/00
CPC分类号： H03M3/386 , H03M3/40 , H03M3/414
摘要： An analog to digital conversion circuit comprises a first digital noise cancellation filter (16) configured to provide a signal to cancel quantization noise from an analog to digital converted output signal. In a calibration phase a second digital noise cancellation filter (26) is has an input coupled to an input of the first digital noise cancellation filter (16). Mutually different sets of at least one-filter coefficients are programmed in the first and second digital noise canceling filters (16, 26). A difference is computed of averaged size indications of digital output signals derived using signals from the first and second digital noise cancellation filters (16, 26) using the same input signal. Updates of the sets of at least one filter coefficients are adapted dependent on the difference between the averaged size indications.
摘要翻译：模数转换电路包括第一数字噪声消除滤波器（16），其被配置为提供从模数转换输出信号消除量化噪声的信号。在校准阶段，第二数字噪声消除滤波器（26）具有耦合到第一数字噪声消除滤波器（16）的输入的输入。至少一个滤波器系数的相互不同的集合被编程在第一和第二数字噪声消除滤波器（16,26）中。使用相同的输入信号计算使用来自第一和第二数字噪声消除滤波器（16,26）的信号导出的数字输出信号的平均尺寸指示的差异。至少一个滤波器系数的集合的更新取决于平均尺寸指示之间的差异。

4. 发明申请

WO2006087667A1 AD CONVERTER ARRANGEMENT 审中-公开
标题翻译： AD转换器布置
公开(公告)号：WO2006087667A1
公开(公告)日：2006-08-24
申请号：PCT/IB2006/050463
申请日：2006-02-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PELGROM, Marcel , PHILIPS, Kathleen , NUIJTEN, Petrus, A., C., M. , ROOVERS, Raf, L., J. , BREEMS, Lucien, J.
发明人： PELGROM, Marcel , PHILIPS, Kathleen , NUIJTEN, Petrus, A., C., M. , ROOVERS, Raf, L., J. , BREEMS, Lucien, J.
IPC分类号： H03M3/00
CPC分类号： H03M3/418
摘要： In an AD converter a primary ΣΔ-modulator digitizes the analog input signal. The quantization noise generated thereby is isolated in the analog domain and digitized in a secondary ΣΔ-modulator. The quantization noise so digitized by the secondary ΣΔ-modulator is subtracted from the quantization noise in the output of the primary ΣΔ-modulator. Because the quantization noise generated by the primary ΣΔ-modulator is subject to filtering (shaping) the quantization noise digitized in the secondary ΣΔ-modulator should also be filtered. This is performed by similar filtering in the feedback path of the secondary ΣΔ-modulator.
摘要翻译：在AD转换器中，主S？调制器将模拟输入信号数字化。由此产生的量化噪声在模拟域中被隔离，并在次级S +调制器中数字化。在主Sα-调制器的输出中从量化噪声中减去由次级S-调制器数字化的量化噪声。由于由主Sα-调制器产生的量化噪声进行滤波（整形），所以也必须对二次S 1调制器中数字化的量化噪声进行滤波。这通过在次级Sδ调制器的反馈路径中的类似滤波来执行。

5. 发明申请

WO2003065590A3 ELECTRONIC CIRCUIT WITH A SIGMA DELTA A/D CONVERTER 审中-公开
公开(公告)号：WO2003065590A3
公开(公告)日：2003-08-07
申请号：PCT/IB2002/005730
申请日：2002-12-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN VELDHOVEN, Robert, G., M. , BREEMS, Lucien, J. , DIJKMANS, Eise, C.
发明人： VAN VELDHOVEN, Robert, G., M. , BREEMS, Lucien, J. , DIJKMANS, Eise, C.
IPC分类号： H03M3/02
摘要： The A/D converter has a digital output for outputting a digital output signal selected from a set of three or more available values. A feedback loop generates the digital output signal so that a time averaged difference between an analog input signal and an analog feedback signal representative of the digital output signal is minimized. A feedback signal generator generates successive signal levels of the feedback signal. A return to zero switch inserts predetermined return to zero levels between the signal levels in the feedback signal. The return to zero switch is also used to provide the signal level for one of the available values.

6. 发明申请

WO2007069178A3 RADIO FREQUENCY ΣΔ-MODULATOR 审中-公开
公开(公告)号：WO2007069178A3
公开(公告)日：2007-06-21
申请号：PCT/IB2006/054733
申请日：2006-12-11
申请人： NXP B.V. , BREEMS, Lucien, J. , LEENAERTS, Domine, M., W.
发明人： BREEMS, Lucien, J. , LEENAERTS, Domine, M., W.
IPC分类号： H03M3/00
摘要： A radio-frequency ΣΔ-modulator comprises a first mixer in the forward path for down-converting the signals in this forward path with a local oscillator frequency and a second mixer in the feedback path for up-converting the feedback signal with the same local oscillator frequency. Delays between the two mixing operations cause a loss of gain in the loop of the ΣΔ-modulator. An adjustable amplifier in the feedback path compensates for this loss of gain.

7. 发明申请

WO2007066274A1 ELECTRONIC QUADRATURE DEVICE 审中-公开
标题翻译：电子平台设备
公开(公告)号：WO2007066274A1
公开(公告)日：2007-06-14
申请号：PCT/IB2006/054572
申请日：2006-12-04
申请人： NXP B.V. , BREEMS, Lucien, J. , RUTTEN, Robert, A., J., A. , REEFMAN, Derk
发明人： BREEMS, Lucien, J. , RUTTEN, Robert, A., J., A. , REEFMAN, Derk
IPC分类号： H03M3/02
CPC分类号： H03D3/007
摘要： An electronic quadrature device is provided comprising at least one I signal path (I) and at least one Q signal path (Q); at least one first sigma-delta modulator (DSDMI) and at least one first digital/analog converter unit (DACI) arranged in the at least one I signal path (I); and at least one second sigma-delta modulator (DSDMQ) and at least one second digital/analog converter unit (DACQ) arranged in the at least one Q signal path (Q). The at least one first sigma-delta modulator (DSDMI) is coupled to the at least one second sigma- delta modulator (DSDMQ) via at least one complex signal path (C1-C4) to implement a complex filter.
摘要翻译：提供电子正交装置，其包括至少一个I信号路径（I）和至少一个Q信号路径（Q）; 至少一个第一Σ-Δ调制器（DSDMI）和至少一个第一数字/模拟转换器单元（DACI），布置在所述至少一个I信号路径（I）中; 以及布置在所述至少一个Q信号路径（Q）中的至少一个第二Σ-Δ调制器（DSDMQ）和至少一个第二数字/模拟转换器单元（DACQ）。所述至少一个第一Σ-Δ调制器（DSDMI）经由至少一个复信号路径（C1-C4）耦合到所述至少一个第二Σ-Δ调制器（DSDMQ），以实现复数滤波器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式