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1. 发明申请

WO2007074111A1 RELIABILITY IMPROVEMENT OF METAL-INTERCONNECT STRUCTURE BY CAPPING SPACERS 审中-公开
标题翻译：金属互连结构的可靠性改进
公开(公告)号：WO2007074111A1
公开(公告)日：2007-07-05
申请号：PCT/EP2006/069911
申请日：2006-12-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , ST MICROELECTRONICS CROLLES 2 SAS , GOSSET, Laurent , ARNAL, Vincent , AIMADEDDINE, Mohamed , TORRES, Joaquin
发明人： GOSSET, Laurent , ARNAL, Vincent , AIMADEDDINE, Mohamed , TORRES, Joaquin
IPC分类号： H01L21/768 , H01L23/52
CPC分类号： H01L23/53238 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76852 , H01L21/76865 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a metal-interconnect structure for electrically connecting integrated-circuit elements in an integrated-circuit device. It solves several problems of operational reliabilit y in damascene interconnect structures, due to corner effects and structural defects present at top edges of interconnect lines fabricated according to prior-art processing technologies. In alternative configurations of the metal interconnect structure, capping spacers (334) are arranged abutting and covering outer top edges (316c) of interconnect lines (304) or lateral barrier liners (316), respectively. The interconnect structure of the invent ion eliminates the negative influence of these critical regio ns in the metal-interconnect structure on the operational reliability of an integrated-circuit device.
摘要翻译：本发明涉及用于将集成电路器件中的集成电路元件电连接的金属互连结构。由于拐角效应和根据现有技术的加工技术制造的互连线的顶部边缘存在的结构缺陷，它解决了镶嵌互连结构中操作可靠性的几个问题。在金属互连结构的替代配置中，封盖间隔物（334）分别布置成邻接和覆盖互连线（304）或侧向阻挡衬里（316）的外顶边缘（316c）。本发明的互连结构消除了金属互连结构中的这些关键区域对集成电路器件的操作可靠性的负面影响。

2. 发明申请

WO2008028851A1 CONTROL OF CARBON NANOSTRUCTURE GROWTH IN AN INTERCONNECT STRUCTURE 审中-公开
标题翻译：碳互连结构中碳纳米管生长的控制
公开(公告)号：WO2008028851A1
公开(公告)日：2008-03-13
申请号：PCT/EP2007/058999
申请日：2007-08-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , ST MICROELECTRONICS (CROLLES 2) SAS , GOSSET, Laurent , TORRES, Joaquin
发明人： GOSSET, Laurent , TORRES, Joaquin
IPC分类号： H01L29/06 , H01L21/768
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/76831 , H01L21/76879 , H01L29/0673 , H01L29/0676 , H01L2221/1094
摘要： An interconnect structure on a substrate is provided. The interconnect structure comprises electrically conductive interconnect elements on at least two interconnect levels on or above a substrate level. In the interconnect structure of the invention, at least one electrically conductive via connects a first interconnect element on one interconnect level or on the substrate level to a second interconnect element on a different interconnect level. The via extends in a via opening of a first dielectric layer and comprises an electrically conductive via material that contains electrically conductive cylindrical carbon nanostructures. At least one cover-layer segment reaches into a lateral extension of the via opening and defines a via aperture that is small enough to prevent a penetration of the carbon nanostructures through the via aperture. This structure enhances control of carbon nanostructure growth in a height direction during fabrication of the interconnect structure.
摘要翻译：提供了衬底上的互连结构。互连结构包括在衬底层上或上方的至少两个互连层上的导电互连元件。在本发明的互连结构中，至少一个导电通孔将一个互连层上的第一互连元件或衬底层上的第一互连元件连接到不同互连层上的第二互连元件。通孔在第一电介质层的通孔中延伸，并且包括含有导电圆柱形碳纳米结构的导电通孔材料。至少一个覆盖层段到达通孔开口的横向延伸部分，并限定通孔孔，其足够小以防止碳纳米结构穿过通孔。该结构在互连结构的制造期间增强了在高度方向上碳纳米结构生长的控制。

3. 发明申请

WO2008065125A1 FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS 审中-公开
标题翻译：包含导电元件的扩散阻挡层的制造
公开(公告)号：WO2008065125A1
公开(公告)日：2008-06-05
申请号：PCT/EP2007/062905
申请日：2007-11-27
申请人： NXP B.V. , ST MICROELECTRONICS (CROLLES 2) SAS , TORRES, Joaquin , GOSSET, Laurent , ARNAL, Vincent , CHHUN, Sonarith
发明人： TORRES, Joaquin , GOSSET, Laurent , ARNAL, Vincent , CHHUN, Sonarith
IPC分类号： H01L21/768 , H01L21/321 , H01L23/532
CPC分类号： H01L21/76849 , H01L21/7682 , H01L21/76822 , H01L21/76826 , H01L21/76829 , H01L21/76856 , H01L21/76867 , H01L21/76886 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a self-aligned diffusion-barrier cap on a Cu- containing conductive element in an integrated-circuit device comprises: - providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface; - depositing a metal layer on the exposed surface of conductive element; - inducing diffusion of metal from the metal layer into a top section of the conductive element; - removing the remaining metal layer; - letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.
摘要翻译：一种用于在集成电路器件中的含Cu导电元件上制造自对准扩散阻挡帽的方法包括： - 提供具有横向插入电介质层并具有暴露表面的含Cu导电元件的衬底; - 在导电元件的暴露表面上沉积金属层; - 诱导金属从金属层扩散到导电元件的顶部; - 去除剩余的金属层; - 使导电元件的顶部中的扩散金属和第二组分的颗粒彼此反应，以便构成覆盖导电元件的化合物。选择金属层和第二组分的金属，使得该化合物形成抵抗Cu扩散的扩散阻挡层。实现了集成电路器件的互连叠层中介电材料的介电常数的降低。

4. 发明申请

WO2008107419A1 FORMATION OF A RELIABLE DIFFUSION-BARRIER CAP ON A CU-CONTAINING INTERCONNECT ELEMENT HAVING GRAINS WITH DIFFERENT CRYSTAL ORIENTATIONS 审中-公开
标题翻译：在具有不同晶体取向的颗粒的含CU连接元件上形成可靠的扩散阻挡层
公开(公告)号：WO2008107419A1
公开(公告)日：2008-09-12
申请号：PCT/EP2008/052565
申请日：2008-03-03
申请人： NXP B.V. , ST MICROELECTRONICS (CROLLES 2) SAS , TORRES, Joaquin , GOSSET, Laurent , CHHUN, Sonarith , ARNAL, Vincent
发明人： TORRES, Joaquin , GOSSET, Laurent , CHHUN, Sonarith , ARNAL, Vincent
IPC分类号： H01L21/768 , H01L21/321
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76867 , H01L21/76889
摘要： The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystalorientations, comprisesselectively incorporating Si into only a first set of crystallites withat least one first crystalorientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier- cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element.
摘要翻译：本发明涉及一种在含Cu互连元件上制造扩散阻挡帽的方法，该方法具有至少两种不同晶体取向的晶体，其包括仅将第一组晶体中的Si并入至少一种第一晶体取向中，条件，并且随后选择性地形成包含CuSi和第一扩散阻挡层部分的第一粘附层部分，仅在第一组微晶上形成第一屏蔽帽部分，随后选择性地将Si并入仅第二组的微晶，使用与第一工艺条件不同的第二工艺条件，以及在互连元件的第二组微晶上形成包含含Si的第二扩散阻挡层部分的第二阻挡帽部分。该处理改善了扩散阻挡帽的性质，并确保了互连元件上的扩散阻挡层的连续形成。

5. 发明申请

WO2008028850A1 CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES 审中-公开
标题翻译：用于集成电路设备中铜的CuSiN / SiN扩散阻挡层
公开(公告)号：WO2008028850A1
公开(公告)日：2008-03-13
申请号：PCT/EP2007/058998
申请日：2007-08-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , ST MICROELECTRONICS (CROLLES 2) SAS , JOURDAN, Nicolas , GOSSET, Laurant Georges , TORRES, Joaquin
发明人： JOURDAN, Nicolas , GOSSET, Laurant Georges , TORRES, Joaquin
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76831 , H01L21/76846 , H01L21/76849 , H01L21/76855 , H01L21/76867 , H01L21/76873 , H01L21/76877 , H01L21/76886 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the invention has a diffusion-barrier layer stack, which comprises, in a direction from the Copper-containing feature to the dielectric layer, a CuSiN layer and a SiN layer. This layer combinat ion provides an efficient barrier for suppressing Copper diffusion from the feature into the dielectric layer. Furthermore, a CuSiN/SiN layer sequence provides an improved adhesion between the layers of the diffusion-barrier layer stack and the dielectric layer, and thus improves the electromigration performance of the integrated-circuit device during operation. Therefore, the reliability of device operation and the lifetime of the integrate- circuit device are improved in comparison with prior-art devices. The invention further relates to a method for fabricating such an integrated-circuit device.
摘要翻译：本发明涉及在电介质层中具有至少一个含铜特征的集成电路器件，以及布置在该特征与该介电层之间的扩散阻挡层堆叠。本发明的集成电路器件具有扩散阻挡层堆叠，其包括在从含铜特征到电介质层的方向上具有CuSiN层和SiN层。该层组合离子提供了有效的屏障，用于抑制从特征进入电介质层的铜扩散。此外，CuSiN / SiN层序列提供了扩散阻挡层堆叠层和电介质层之间的改进的粘合性，从而提高了集成电路器件在操作期间的电迁移性能。因此，与现有技术的器件相比，器件操作的可靠性和集成电路器件的寿命得到改善。本发明还涉及一种用于制造这种集成电路器件的方法。

6. 发明申请

WO2008074672A1 IMPROVING ADHESION OF DIFFUSION BARRIER ON CU CONTAINING INTERCONNECT ELEMENT 审中-公开
标题翻译：扩展阻塞器对包含互连元件的粘附改善
公开(公告)号：WO2008074672A1
公开(公告)日：2008-06-26
申请号：PCT/EP2007/063552
申请日：2007-12-07
申请人： NXP B.V. , ST MICROELECTRONICS (CROLLES 2) SAS , GOSSET, Laurent Georges , TORRES, Joaquin , CHHUN, Sonarith
发明人： GOSSET, Laurent Georges , TORRES, Joaquin , CHHUN, Sonarith
IPC分类号： H01L21/321 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76849 , H01L21/31155 , H01L21/76825 , H01L21/76834 , H01L21/76867 , H01L21/76886 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a method for fabricating a semiconductor device. For improving the adhesion between a copper-containing interconnect element and a diffusion barrier on top of it, a first dielectric layer (108) of a first dielectric material is deposited on an exposed surface (102.1) of the interconnect element. Susequently, particles (110) are implanted into the first dielectric layer and the interconnect element (102) so as to let the interconnect material mix with the first dielectric material in a first interface region (102.2) between the interconnect element and thefirst dielectric layer.
摘要翻译：本发明涉及半导体器件的制造方法。为了改善含铜互连元件和其顶部的扩散阻挡层之间的粘附性，第一介电材料的第一介电层（108）沉积在互连元件的暴露表面（102.1）上。很显然，将粒子（110）注入到第一介电层和互连元件（102）中，以使互连材料与互连元件和第一介电层之间的第一界面区域（102.2）中的第一介电材料混合。

7. 发明申请

WO2007099428A1 METAL INTERCONNECTS IN A DIELECTRIC MATERIAL 审中-公开
标题翻译：电介质材料中的金属互连
公开(公告)号：WO2007099428A1
公开(公告)日：2007-09-07
申请号：PCT/IB2007/000455
申请日：2007-02-26
申请人： STMICROELECTRONICS (CROLLES 2) SAS , KONINKLIJKE PHILIPS ELECTRONICS N.V. , TORRES, Joaquin , ARNAL, Vincent , GOSSET, Laurent-Georges , BESLING, Wim
发明人： TORRES, Joaquin , ARNAL, Vincent , GOSSET, Laurent-Georges , BESLING, Wim
IPC分类号： H01L21/768
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76844
摘要： Method for manufacturing a semiconductor device comprising an interconnect comprising electrically conductive portions, in a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The method further comprises removing exposed portions of the dielectric layer which form the side walls of the trench and depositing a dielectric liner on the side walls of the trench, said liner being made of a second dielectric material.
摘要翻译：在由第一介电材料制成的电介质层中制造半导体器件的方法，所述半导体器件包括包括导电部分的互连。在电介质层中形成沟槽。该方法还包括去除形成沟槽侧壁的电介质层的暴露部分，并在沟槽的侧壁上沉积电介质衬垫，所述衬垫由第二电介质材料制成。

8. 发明申请

WO2007083237A1 INTEGRATION OF SELF-ALIGNED TRENCHES IN-BETWEEN METAL LINES 审中-公开
标题翻译：金属线之间自对准沟槽的集成
公开(公告)号：WO2007083237A1
公开(公告)日：2007-07-26
申请号：PCT/IB2007/000162
申请日：2007-01-11
申请人： STMICROELECTRONICS (CROLLES 2) SAS , KONINKLIJKE PHILIPS ELECTRONICS N.V. , TORRES, Joaquin , GOSSET, Laurent-Georges
发明人： TORRES, Joaquin , GOSSET, Laurent-Georges
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/76885 , H01L23/5222 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing (42) an intertrack dielectric deposited on an interconnect structure surface to control the height between the top surface of a metal line of the interconnect surface and the surface of the intertrack dielectric; depositing (44) a dielectric liner on the interconnect surface; removing (46) at least part of the dielectric liner on the interconnect surface; successively repeating (48) the deposition of the dielectric liner and the removal of the dielectric liner on the interconnect surface in so far as the interconnect surface is sufficiently protected by a remaining dielectric liner for forming of the plurality of air cavity trenches; and forming (50) at least one air cavity trench in-between the metal lines by etching the intertrack dielectric material.
摘要翻译：本发明提供了一种改进的形成气腔以克服IC通孔未对准问题的方法。在集成电路的金属线之间形成气腔沟槽的方法包括以下步骤：部分地移除（42）沉积在互连结构表面上的叠层电介质以控制互连表面的金属线的顶表面之间的高度和内部电介质的表面; 在互连表面上沉积（44）电介质衬里; 去除（46）所述互连表面上的所述电介质衬里的至少一部分; 只要互连表面被剩余的电介质衬垫充分保护以形成多个气穴沟槽，就连续重复（48）电介质衬垫的沉积和电介质衬垫在互连表面上的移除; 以及通过蚀刻所述叠层电介质材料在所述金属线之间形成（50）至少一个空气腔沟槽。

9. 发明申请

WO2008040706A1 MIM CAPACITOR 审中-公开
标题翻译： MIM电容器
公开(公告)号：WO2008040706A1
公开(公告)日：2008-04-10
申请号：PCT/EP2007/060400
申请日：2007-10-01
申请人： STMICROELECTRONICS CROLLES 2 SAS , NXP B.V. , FARCY, Alexis , THOMAS, Maryline , TORRES, Joaquin , CHHUN, Sonarith , GOSSET, Laurent-Georges
发明人： FARCY, Alexis , THOMAS, Maryline , TORRES, Joaquin , CHHUN, Sonarith , GOSSET, Laurent-Georges
IPC分类号： H01G4/005 , H01G4/06
CPC分类号： H01G4/005 , H01G4/008 , H01L28/91
摘要： The invention concerns a method of forming a metal- insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having a form comprising at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.
摘要翻译：本发明涉及一种形成金属 - 绝缘体 - 金属电容器的方法，该金属 - 绝缘体 - 金属电容器具有由电介质层隔开的顶板和底板，所述顶板和底板中的一个具有包括延伸到另一个中的另一个中的相应空腔中的至少一个突起的形式所述方法包括在基底表面上生长一个或多个纳米纤维的步骤。

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