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    • 8. 发明申请
    • DYNAMIC FREQUENCY MEMORY CONTROL
    • 动态频率记忆控制
    • WO2011029734A1
    • 2011-03-17
    • PCT/EP2010/062568
    • 2010-08-27
    • ST-ERICSSON SAYERMALAYEU, Siarhei
    • YERMALAYEU, Siarhei
    • G06F13/16
    • G06F13/1689G06F13/1694Y02D10/14
    • A memory controller (40) is adaptable to scaling of a system clock frequency, to enable another device (10) to access a memory (20), and has a part for outputting control signals having some timing characteristics not entirely scalable with scaling of the system clock frequency. In response to an indication of a change in a frequency of the system clock, the memory controller adapts the part autonomously to enable it to output new digital memory control signals synchronized to the changed system clock and which also have the non scalable timing characteristics. This avoids the need for the processor to adapt the memory controller. Hence the adaptation can be carried out more quickly, leading to less disruption to other parts of the system and means the frequency scaling can be carried out more often.
    • 存储器控制器(40)适于缩放系统时钟频率,以使得另一设备(10)能够访问存储器(20),并且具有用于输出具有某些定时特性的控制信号的部分,该定时特性不完全可缩放, 系统时钟频率。 响应于系统时钟的频率变化的指示,存储器控制器自适应地调整该部分以使其能够输出与改变的系统时钟同步的新的数字存储器控制信号,并且还具有不可缩放的定时特性。 这避免了处理器适应存储器控制器的需要。 因此,可以更快地执行适配,导致系统其他部分的中断更少,意味着可以更频繁地执行频率缩放。