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1. 发明申请

WO2006085273A1 LOW-POWER REGISTER ARRAY FOR FAST SHIFT OPERATIONS 审中-公开
标题翻译：低功率寄存器阵列用于快速移位操作
公开(公告)号：WO2006085273A1
公开(公告)日：2006-08-17
申请号：PCT/IB2006/050415
申请日：2006-02-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS, N.V. , U.S. PHILIPS CORPORATION , BI, Lei , PU, Tianyan
发明人： BI, Lei , PU, Tianyan
IPC分类号： G06F5/10
CPC分类号： G06F5/10
摘要： A data register (300) for use in a computer comprises a clock terminal (310) configured to receive a clock signal. A plurality of registers (320) are configured to selectively store data. A data input circuit (330) is coupled to the registers and configured to receive input data and selectively deliver the input data to the registers. A data output circuit (340) is coupled to the data registers and configured to selectively output the output data. A selector (350) is coupled to the data input circuit and the data output circuit, and configured to permit the input data to enter selected registers through the data input circuit and permit selected registers to output data through the data output circuit. The invention provides an efficient technique for loading the shift registers without a large number of simultaneous serial shifts. The result is a power-efficient device that achieves high performance objectives while minimizing power consumption.
摘要翻译：用于计算机的数据寄存器（300）包括被配置为接收时钟信号的时钟端子（310）。多个寄存器（320）被配置为选择性地存储数据。数据输入电路（330）耦合到寄存器并被配置为接收输入数据并选择性地将输入数据传送到寄存器。数据输出电路（340）耦合到数据寄存器并被配置为选择性地输出输出数据。选择器（350）耦合到数据输入电路和数据输出电路，并且被配置为允许输入数据通过数据输入电路输入所选择的寄存器，并允许所选择的寄存器通过数据输出电路输出数据。本发明提供了一种用于在没有大量同时串行移位的情况下加载移位寄存器的有效技术。结果是能够实现高性能目标的功率高效的器件，同时最大限度地降低功耗。

2. 发明申请

WO2006103601A3 CANONICAL SIGNED DIGIT MULTIPLIER 审中-公开
公开(公告)号：WO2006103601A3
公开(公告)日：2006-10-05
申请号：PCT/IB2006/050892
申请日：2006-03-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PU, Tianyan , BI, Lei
发明人： PU, Tianyan , BI, Lei
IPC分类号： G06F7/533
摘要： A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and it is controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value. Variable shift blocks are each connected to receive an input from a respective one of said multiplexers, and are each adapted to shift their received input by a first bit shift value or a second bit shift value, depending on the values of the respective pair of bits of the selected constant value, wherein the first bit shift value and the second bit shift value differ by 1. The multiplier also includes combination circuitry, for receiving the outputs from the plurality of shift blocks, and for combining the outputs from the plurality of shift blocks and applying further bit shifts, to form an output value equal to the result of multiplying the input data value by the selected constant value.

3. 发明申请

WO2006109240A2 FAST FOURIER TRANSFORM ARCHITECTURE 审中-公开
标题翻译：快速FOURIER变形架构
公开(公告)号：WO2006109240A2
公开(公告)日：2006-10-19
申请号：PCT/IB2006/051101
申请日：2006-04-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PU, Tianyan , BI, Lei , TJIA, Jerome
发明人： PU, Tianyan , BI, Lei , TJIA, Jerome
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A last fourier transform architecture has parallel data processing paths. Input data is applied to the parallel data processing paths in a repeating sequence, and processed in those paths. Data sequencers are used to combine the outputs from the data processing paths into the required sequence.
摘要翻译：最后一个傅立叶变换架构具有并行数据处理路径。输入数据以重复序列应用于并行数据处理路径，并以这些路径进行处理。数据定序器用于将来自数据处理路径的输出组合到所需的序列中。

4. 发明申请

WO2008068669A1 IMPROVING PERFORMANCE IN A TIME-FREQUENCY INTERLEAVED ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING SYSTEM 审中-公开
标题翻译：提高时频间隔正交频分复用系统的性能
公开(公告)号：WO2008068669A1
公开(公告)日：2008-06-12
申请号：PCT/IB2007/054823
申请日：2007-11-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS, N.V. , GADDAM, Vasanth, R. , PU, Tianyan , ZHANG, Yifeng
发明人： GADDAM, Vasanth, R. , PU, Tianyan , ZHANG, Yifeng
IPC分类号： H04L25/02 , H04L27/26
CPC分类号： H04L25/022 , H04L27/2649
摘要： In one embodiment, a TFI-OFDM receiver system (22) is able to more reliably decode the information bits by estimating the noise variance associated with the channel and using these estimates in mitigating in-band interference. In another embodiment, there is a TFI-OFDM receiver system (66) that is able to update the estimated channel impulse response and the noise variance by generating reference OFDM symbols from the received header symbols, the band hopping pattern provided by the TFC number associated with the communication link, the estimated channel impulse response and the noise variance estimates and symbols generated from a FFT processor (30).
摘要翻译：在一个实施例中，TFI-OFDM接收机系统（22）能够通过估计与信道相关联的噪声方差并且在减轻带内干扰中使用这些估计来更可靠地解码信息比特。在另一个实施例中，存在TFI-OFDM接收机系统（66），其能够通过从接收到的标题符号生成参考OFDM符号来更新所估计的信道脉冲响应和噪声方差，所述TFC号码相关联提供的跳频模式通信链路，估计信道脉冲响应和从FFT处理器（30）产生的噪声方差估计和符号。

5. 发明申请

WO2008041160A2 METHOD AND APPARATUS FOR GENERATING DATA PACKETS FOR TRANSMISSION IN AN OFDM COMMUNICATION SYSTEM 审中-公开
标题翻译：用于在OFDM通信系统中生成用于传输的数据分组的方法和设备
公开(公告)号：WO2008041160A2
公开(公告)日：2008-04-10
申请号：PCT/IB2007/053933
申请日：2007-09-27
申请人： NXP B.V. , PU, Tianyan
发明人： PU, Tianyan
CPC分类号： H04L27/2626 , H04L27/2602 , H04W52/0212 , Y02D70/142 , Y02D70/144 , Y02D70/168
摘要： Method and apparatus for generating data packets for transmission in an orthogonal frequency division modulated communication system, in which preamble sequence for each packet is generated in the frequency domain or the time domain depending on at least two conditions to save power consumption and enable implementation in a single CMOS chip.
摘要翻译：用于在正交频分调制通信系统中产生用于传输的数据分组的方法和设备，其中根据至少两个条件在频域或时域中产生每个分组的前导码序列节省功耗，并可在单个CMOS芯片中实现。

6. 发明申请

WO2008032261A2 DEINTERLEAVER 审中-公开
标题翻译：解交织
公开(公告)号：WO2008032261A2
公开(公告)日：2008-03-20
申请号：PCT/IB2007/053643
申请日：2007-09-10
申请人： NXP B.V. , PU, Tianyan , SAWITZKI, Sergei, V.
发明人： PU, Tianyan , SAWITZKI, Sergei, V.
IPC分类号： H03M13/27
CPC分类号： H03M13/2796 , H03M13/271 , H03M13/276
摘要： A deinterleaver for a wireless communication device is provided that is simple and inexpensive to implement. In particular, a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme is provided, the deinterleaver comprising preprocessing means for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator for the at least one memory, the generator being adapted to determine the addresses in the at least one memory that pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.
摘要翻译：提供了一种用于无线通信设备的解交织器，其实现简单且便宜。特别地，提供了一种用于对表示使用多级交织方案交织的多个符号的数据比特流进行解交织的解交织器，该解交织器包括用于将流中的数据比特排序成对的预处理装置，该对中的数据位是来自符号的连续数据位; 至少一个用于存储配对位的存储器，使得每对数据位被存储在存储器中的相应位置中; 以及用于所述至少一个存储器的读取和写入地址生成器，所述发生器适于确定所述至少一个存储器中要存储的数据位对的地址，并且确定所述至少一个存储器中的地址一对数据位将被读取。

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