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1. 发明申请

WO0005766A2 SILICON-ON-INSULATOR (SOI) HYBRID TRANSISTOR DEVICE STRUCTURE 审中-公开
标题翻译：硅绝缘体（SOI）混合晶体管器件结构
公开(公告)号：WO0005766A2
公开(公告)日：2000-02-03
申请号：PCT/IB9901205
申请日：1999-06-28
申请人： KONINKL PHILIPS ELECTRONICS NV , PHILIPS SVENSKA AB
发明人： LETAVIC THEODORE , MUKHERJEE SATYEN , EMMERIK ARNO , VAN ZWOL JOHANNES
IPC分类号： H01L27/08 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/78 , H01L29/786 , H01L29/772
CPC分类号： H01L29/7394 , H01L29/0696 , H01L29/0834
摘要： A silicon-on-insulator (SOI) hybrid transistor device structure includes a substrate, a buried insulating layer on the substrate, and a hybrid transistor device structure formed in a semiconductor surface layer on the buried insulating layer. The hybrid transistor device structure may advantageously include at least one MOS transistor structure and at least one conductivity modulation transistor structure electrically connected in parallel. In a particularly advantageous configuration, the MOS transistor structure may be an LDMOS transistor structure and the conductivity modulation transistor structure may be an LIGB transistor structure, with the hybrid transistor device being formed in a closed geometry configuration. This closed geometry configuration may have both substantially curved segments and substantially straight segments, with MOS structures being formed in the curved segments and conductivity modulation transistor structures being formed in the straight segments. Hybrid transistor device structures in accordance with the invention feature excellent operating characteristics in high current, high voltage circuit applications, and in particular in source-follower circuit applications.
摘要翻译：绝缘体上硅（SOI）混合晶体管器件结构包括衬底，衬底上的掩埋绝缘层以及形成在掩埋绝缘层上的半导体表面层中的混合晶体管器件结构。混合晶体管器件结构可以有利地包括至少一个MOS晶体管结构和并联电连接的至少一个导电调制晶体管结构。在特别有利的配置中，MOS晶体管结构可以是LDMOS晶体管结构，并且导电调制晶体管结构可以是LIGB晶体管结构，其中混合晶体管器件形成为封闭的几何结构。这种闭合的几何构型可以具有基本上弯曲的段和基本上直的段，其中MOS结构形成在弯曲段中，并且导电调制晶体管结构形成在直段中。根据本发明的混合晶体管器件结构在高电流，高压电路应用中尤其是源极跟随器电路应用中具有优异的工作特性。

2. 发明申请

WO0145142A3 LATERAL INSULATED-GATE BIPOLAR TRANSISTOR (LIGBT) DEVICE IN SILICON-ON-INSULATOR (SOI) TECHNOLOGY 审中-公开
标题翻译：硅绝缘体（SOI）技术中的横向绝缘栅双极型晶体管（LIGBT）器件
公开(公告)号：WO0145142A3
公开(公告)日：2001-12-06
申请号：PCT/EP0011929
申请日：2000-11-29
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： PETRUZZELLO JOHN , LETAVIC THEODORE , VAN ZWOL JOHANNES
IPC分类号： H01L29/786 , H01L29/06 , H01L29/423 , H01L29/739
CPC分类号： H01L29/7394 , H01L29/0696 , H01L29/42368
摘要： A lateral thin-film Silicon-On-Insulator (SOI) device (20) includes a semiconductor substrate (22), a buried insulating layer (24) on the substrate and a Lateral Insulated Gate Bipolar Transistor (LIGBT) device in an SOI layer on the buried insulating layer (24) and having a source region (28) of a first conductivity type formed in a body region (30) of a second conductivity type opposite to that of the first and a body contact region (40) of the second conductivity type in the body region (30) and connected to the source region (28). A lateral drift region (32a) of a first conductivity type is provided adjacent the body region (30) and forms a lightly-doped drain region, and a drain contact region (34) of the first conductivity type is provided laterally spaced apart from the body region by the drift region with an anode region (42) of the second conductivity type in the drain region and connected to the drain contact region (34). A gate electrode (36) is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region (32a) adjacent the body region (30), with the gate electrode (36) being at least substantially insulated from the body region and drift region by a surface insulation region (38). Improved device performance is achieved by making a dimension of the source region in a direction normal to a direction of current flow between the source region (28) and the drain contact region (34) greater than a corresponding dimension of the drain contact region and of the anode region (42).
摘要翻译：横向薄膜绝缘体上硅（SOI）器件（20）包括半导体衬底（22），衬底上的掩埋绝缘层（24）和SOI层中的横向绝缘栅双极晶体管（LIGBT）器件在所述掩埋绝缘层（24）上并且具有形成在与所述第一导电类型的所述第一导电类型的所述第一导电类型的本体区域（30）相反的第二导电类型的源区域（28）和所述第一导电类型的本体接触区域（40）在所述体区域（30）中并连接到所述源极区域（28）的第二导电类型。第一导电类型的横向漂移区域（32a）与本体区域（30）相邻设置并形成轻掺杂漏极区域，并且第一导电类型的漏极接触区域（34）与第一导电类型的漏极接触区域通过所述漂移区与所述漏极区中的所述第二导电类型的阳极区（42）连接并且与所述漏极接触区（34）连接。栅电极（36）设置在体区的一部分上，其中在工作期间形成沟道区并且在与体区（30）相邻的横向漂移区（32a）的一部分上延伸，栅电极（ 36）通过表面绝缘区域（38）至少基本上与本体区域和漂移区域绝缘。通过使在与源极区域（28）和漏极接触区域（34）之间的电流流动方向垂直的方向上的源极区域的尺寸大于漏极接触区域的对应尺寸和阳极区域（42）。

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