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1. 发明申请

WO2019053619A1 OPTOELECTRONIC DEVICE HAVING A BORON NITRIDE ALLOY ELECTRON BLOCKING LAYER AND METHOD OF PRODUCTION 审中-公开
公开(公告)号：WO2019053619A1
公开(公告)日：2019-03-21
申请号：PCT/IB2018/056988
申请日：2018-09-12
申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： LI, Xiaohang , GUO, Wenzhe , SUN, Haiding
IPC分类号： H01L33/04 , H01L27/15
摘要： An optoelectronic device a substrate, a first doped contact layer arranged on the substrate, a multiple quantum well layer arranged on the first doped contact layer, a boron nitride alloy electron blocking layer arranged on the multiple quantum well layer, and a second doped contact layer arranged on the boron nitride alloy electron blocking layer.

2. 发明申请

WO2020157589A1 SEMICONDUCTOR DEVICE WITH A GROUP-III OXIDE ACTIVE LAYER 审中-公开
公开(公告)号：WO2020157589A1
公开(公告)日：2020-08-06
申请号：PCT/IB2020/050268
申请日：2020-01-14
申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： LI, Xiaohang , LIAO, Che-Hao
IPC分类号： H01L21/36
摘要： A method for forming a semiconductor device with a group-III oxide active layer including at least two group-III materials is provided. A group-III oxide substrate is provided and a group-III oxide active layer including at least one group-III material on the group-III oxide substrate is formed on the group-III oxide substrate. A group-III material in the group-III oxide substrate is different from the at least one group-III material in the group-III oxide active layer. The group-III oxide active layer including at least one group-III material and the group-III oxide substrate are annealed at a temperature greater than or equal to 1,000° C so that the group-III material in the group-III oxide substrate diffuses into the group-III oxide active layer to form the group-III oxide active layer including the at least two group-III materials.

3. 发明申请

WO2019155444A1 SEMICONDUCTOR DEVICES WITH TWO III‑OXIDE LAYERS HAVING DIFFERENT PHASES AND METHOD OF PRODUCTION 审中-公开
公开(公告)号：WO2019155444A1
公开(公告)日：2019-08-15
申请号：PCT/IB2019/051125
申请日：2019-02-12
申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： LI, Xiaohang , LI, Kuang-Hui , SUN, Haiding , TOMPA, Gary S. , OKUR, Serdal , SALAGAJ, Thomas
IPC分类号： H01L21/36 , H01L21/02
CPC分类号： H01L21/02565 , H01L21/02483 , H01L21/0262
摘要： A semiconductor device is formed having a second III-oxide layer on a first III-oxide layer. The first III-oxide layer having a first phase is formed by feeding a first group III element precursor, a first oxygen precursor, and molecules including hydrogen and/or chlorine ions into a growth chamber. The second III-oxide layer is formed on the first III-oxide layer by feeding a second group III element precursor, a second oxygen precursor, and molecules including hydrogen and/or chlorine ions into the growth chamber. The second III-oxide layer has a second phase, which is different from the first phase. The molecules including hydrogen and/or chlorine ions are fed at a first flow rate during the formation of the first III-oxide layer and are fed at a second flow rate during the formation of the second III-oxide layer. The first and second flow rates are different flow rates.

4. 发明申请

WO2021105835A1 IDENTIFYING TUNNEL JUNCTIONS HAVING LOW RESISTANCE 审中-公开
公开(公告)号：WO2021105835A1
公开(公告)日：2021-06-03
申请号：PCT/IB2020/060985
申请日：2020-11-20
申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： LI, Xiaohang , LIN, Rongyu
IPC分类号： G06F30/27
摘要： A method for identifying a tunnel junction having a predetermined resistance involves receiving a set of data comprising parameters of a plurality of tunnel junctions. The set of data into first and second subsets of data. A machine learning model is iteratively trained using the first subset of data. Each iteration of the training of the machine learning model minimizes residuals of a previous iteration of the training of the machine learning model. The training is terminated and then the predetermined resistance is input to the final machine learning model, which outputs parameters for a target tunnel junction.

5. 发明申请

WO2021099921A1 LIGHT-EMITTING DEVICE WITH POLARIZATION MODULATED LAST QUANTUM BARRIER 审中-公开
公开(公告)号：WO2021099921A1
公开(公告)日：2021-05-27
申请号：PCT/IB2020/060785
申请日：2020-11-16
申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： LI, Xiaohang , LIU, Zhiyuan
IPC分类号： H01L33/00 , H01L33/06 , H01L33/32
摘要： A light-emitting device (100A) includes doped layer (110) arranged on a substrate (105). The doped layer is n-doped or p-doped. A multiple quantum well (115) is arranged on the doped layer and includes a plurality of adjacent pairs of quantum wells and quantum barriers. An electron blocking layer (130) is arranged on the multiple quantum well. The doped layer (110), the electron blocking layer (130), the quantum wells, and all of the quantum barriers except for the last quantum barrier include a first Ill-nitride alloy. The last quantum barrier includes a second Ill-nitride alloy that is different from the first Ill-nitride alloy. The second Ill-nitride alloy has a bandgap larger than a bandgap of the last quantum well and smaller than a bandgap of the electron blocking layer. An interface between the last quantum barrier and the electron blocking layer (130) exhibits a polarization difference between 0 and 0.012 C/m2.

6. 发明申请

WO2019111153A1 METHODS FOR FORMING GRADED WURTZITE III-NITRIDE ALLOY LAYERS 审中-公开
公开(公告)号：WO2019111153A1
公开(公告)日：2019-06-13
申请号：PCT/IB2018/059631
申请日：2018-12-04
申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： LI, Xiaohang , LIU, Kaikai
IPC分类号： H01L33/02 , H01L33/00 , H01L21/02
CPC分类号： H01L33/025 , H01L21/02389 , H01L21/02458 , H01L21/0251 , H01L21/0254 , H01L33/007 , H01L33/0075
摘要： A method for forming a semiconductor device comprising a graded wurtzite III-nitride alloy layer, including a wurtzite III-nitride alloy, on a second layer. A polarization doping concentration profile is selected for the graded wurtzite III-nitride alloy layer based on an intended function of the semiconductor device. Based on the selected polarization doping concentration profile for the graded wurtzite III-nitride alloy layer, a composition-polarization change rate of the graded wurtzite III-nitride alloy layer and a grading speed of the graded wurtzite III-nitride alloy layer are determined. The composition-polarization change rate and grading speed are based on a composition of first and second elements of the wurtzite III-nitride alloy. The graded wurtzite III- nitride alloy layer is formed on the second layer having the selected polarization doping concentration profile using the determined composition-polarization change rate and grading speed to adjust the composition of the first and second III-nitride elements of the wurtzite III-nitride alloy based on a current position in the graded wurtzite III-nitride alloy layer from the second layer.

7. 发明申请

WO2023042091A1 AMBIPOLAR OXIDE-SEMICONDUCTOR BASED TRANSISTOR AND METHOD OF MANUFACTURING 审中-公开
公开(公告)号：WO2023042091A1
公开(公告)日：2023-03-23
申请号：PCT/IB2022/058660
申请日：2022-09-14
申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： LI, Xiaohang , YUVARAJA, Saravanan
IPC分类号： H01L29/775 , H01L29/786 , H01L29/06 , H01L21/336 , H01L29/24 , H01L29/423 , H01L27/088 , B82Y10/00
摘要： An ambipolar, gate all around, semiconductor-based transistor (600) includes a substrate (602), a first-type channel structure (106) of a first-type material located on the substrate (602), the first-type channel structure (106) having a gate region, a source region, and a drain region, a second-type channel structure (310) of a second- type material completely surrounding the gate region of the first-type channel structure (106), but not present on the source region and the drain region. Furthermore, a dielectric material (108) fully surrounds the second-type material (310), a gate electrode (110) completely surrounds the dielectric material (108)., a source electrode is located on the source region and a drain electrode is located on the drain region. The first and second materials are semiconductor oxides, preferably Ga2O3 and NiO, the first-type material is one of p-or n-type and the second-type material is the other of the p- or n-type.

8. 发明申请

WO2019111161A1 FORMING III-NITRIDE ALLOYS 审中-公开
公开(公告)号：WO2019111161A1
公开(公告)日：2019-06-13
申请号：PCT/IB2018/059643
申请日：2018-12-04
申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： LI, Xiaohang , LIU, Kaikai
IPC分类号： H01L21/02
CPC分类号： H01L21/0254 , H01L21/02617
摘要： A method for forming a semiconductor device involves selecting a substrate on which a wurtzite III-nitride alloy layer will be formed, and a piezoelectric polarization and an effective piezoelectric coefficient for the wurtzite III-nitride alloy layer. It is determined whether there is a wurtzite III-nitride alloy composition satisfying the selected effective piezoelectric coefficient. It is also determined whether there is a thickness for a layer formed from the wurtzite III-nitride alloy composition satisfying the selected piezoelectric polarization based on the selected substrate and the selected effective piezoelectric coefficient. Responsive to the determination that there is a wurtzite III-nitride alloy composition having a lattice constant satisfying the selected effective piezoelectric coefficient and a thickness for the layer formed from the wurtzite III-nitride alloy composition satisfying the selected piezoelectric polarization, the wurtzite III-nitride alloy layer is formed on the substrate having the wurtzite III-nitride alloy composition satisfying the selected effective piezoelectric coefficient and having the thickness satisfying the selected piezoelectric polarization.

9. 发明申请

WO2019073413A1 SEMICONDUCTOR DEVICES HAVING HETEROJUNCTIONS OF A BORON GALLIUM NITRIDE TERNARY ALLOY LAYER AND A SECOND III‑NITRIDE TERNARY ALLOY LAYER 审中-公开
公开(公告)号：WO2019073413A1
公开(公告)日：2019-04-18
申请号：PCT/IB2018/057856
申请日：2018-10-10
申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： LI, Xiaohang , LIU, Kaikai
IPC分类号： H01L21/20
CPC分类号： H01L21/0254 , H01L21/02381 , H01L21/02389 , H01L21/0242 , H01L21/02458
摘要： A method for forming a semiconductor device having a heterojunction of a first III- nitride ternary alloy layer arranged on a second III-nitride ternary alloy layer is provided. A range of concentrations of III-nitride elements for the first and second III- nitride ternary alloy layers is determined so that the absolute value of the polarization difference at the interface of the heterojunction of the first and second III-nitride ternary alloy layers is less than or equal to 0.007 C/m2 or greater than or equal to 0.04 C/m2. Specific concentrations of III-nitride elements for the first and second III- nitride ternary alloy layers are selected from the determined range of concentrations so that the absolute value of the polarization difference at the interface of the heterojunction of the first and second III-nitride ternary alloy layers is less than or equal to 0.007 C/m2 or greater than or equal to 0.04 C/m2. The semiconductor device is formed using the selected specific concentrations of III-nitride elements for the first and second III-nitride ternary alloy layers. The first and second III-nitride ternary alloy layers have a Wurtzite crystal structure. The first III-nitride ternary alloy layer is BGaN and the second III-nitride ternary alloy layer is InGaN, InAlN, BAlN, or AlGaN.

10. 发明申请

WO2019073411A1 SEMICONDUCTOR DEVICES HAVING HETEROJUNCTIONS OF AN INDIUM ALUMINUM NITRIDE TERNARY ALLOY LAYER AND A SECOND III‑NITRIDE TERNARY ALLOY LAYER 审中-公开
公开(公告)号：WO2019073411A1
公开(公告)日：2019-04-18
申请号：PCT/IB2018/057854
申请日：2018-10-10
申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： LI, Xiaohang , LIU, Kaikai
IPC分类号： H01L21/20
CPC分类号： H01L21/0254 , H01L21/02381 , H01L21/02389 , H01L21/0242 , H01L21/02458
摘要： A method for forming a semiconductor device having a heterojunction of a first III- nitride ternary alloy layer arranged on a second III-nitride ternary alloy layer is provided. A range of concentrations of III-nitride elements for the first and second III- nitride ternary alloy layers is determined so that the absolute value of the polarization difference at the interface of the heterojunction of the first and second III-nitride ternary alloy layers is less than or equal to 0.007 C/m2 or greater than or equal to 0.04 C/m2. Specific concentrations of III-nitride elements for the first and second III- nitride ternary alloy layers are selected from the determined range of concentrations so that the absolute value of the polarization difference at the interface of the heterojunction of the first and second III-nitride ternary alloy layers is less than or equal to 0.007 C/m2 or greater than or equal to 0.04 C/m2. The semiconductor device is formed using the selected specific concentrations of III-nitride elements for the first and second III-nitride ternary alloy layers. The first and second III-nitride ternary alloy layers have a Wurtzite crystal structure. The first III-nitride ternary alloy layer is InAlN and the second III-nitride ternary alloy layer is InGaN, AlGaN, BAlN, or BGaN.

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