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1. 发明申请

WO2014013078A1 SEMICONDUCTOR DIE WITH A THROUGH SILICON VIA AND MANUFACTURING PROCESS OF A SUCH VIA 审中-公开
标题翻译：具有通过硅的半导体器件和这种威盛的制造工艺
公开(公告)号：WO2014013078A1
公开(公告)日：2014-01-23
申请号：PCT/EP2013/065354
申请日：2013-07-19
申请人： IPDIA
发明人： TENAILLEAU, Jean-René , VOIRON, Frédéric
IPC分类号： H01L21/768 , H01L23/14 , H01L23/48 , H01L23/498
CPC分类号： H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die according to this invention comprises a via realised in a bulk material (2). The via has an inner metallic conductor (28) isolated by a dielectric layer (17, 20) from a surrounding conductive area (16) formed by a deposited layer. The bulk material (2) is chosen in a set of doped semiconductor materials containing n-type and p-type materials. The surrounding conductive area (16) is in contact with the bulk material (2) and the surrounding conductive area (16) is made from a material chosen in a set of doped semiconductor materials containing n-type and p-type materials, the surrounding conductive area material being from one type among the n-type and the p-type, and the bulk material being from the other type among said n-type and said p-type.
摘要翻译：根据本发明的半导体管芯包括以块状材料（2）实现的通孔。通孔具有由与由沉积层形成的周围导电区域（16）隔离的介电层（17,20）隔离的内部金属导体（28）。散装材料（2）在包含n型和p型材料的一组掺杂半导体材料中选择。周围的导电区域（16）与散装材料（2）接触，并且周围的导电区域（16）由选自包含n型和p型材料的一组掺杂半导体材料中的材料制成，周围导电区域材料是n型和p型中的一种，并且所述散装材料是所述n型和所述p型中的另一种类型。

2. 发明申请

WO2013083714A1 AN INTERPOSER DEVICE 审中-公开
标题翻译：插件设备
公开(公告)号：WO2013083714A1
公开(公告)日：2013-06-13
申请号：PCT/EP2012/074680
申请日：2012-12-06
申请人： IPDIA
发明人： TENAILLEAU, Jean-René , FERRU, Gilles
IPC分类号： H01L23/48 , H01L23/498 , H01L23/14
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/147 , H01L23/49827 , H01L25/167 , H01L27/0814 , H01L33/62 , H01L2224/02372 , H01L2924/1305 , H01L2924/00
摘要： An interposer device The invention relates to an interposer device comprising a doped silicon substrate (1) having an epitaxial layer (24) on a first side and two through vias (11, 12) extending from the first side to a second side opposite to the first side of the doped silicon substrate. Each through via comprises a volume of doped silicon substrate delimited by a surrounding trench (7) extending from the first to the second side of the doped silicon substrate such that said surrounding trench is arranged so as to electrically isolate the doped silicon substrate surrounded by said trench. First and second conductive layers (121, 122) are laid respectively on first and second sides of the first through via so as to be electrically connected together and third and fourth conductive layers (112, 11) are laid respectively on surfaces of the second through via so as to be electrically connected together. The first (122) and third (112) conductive layers are connected together by means of a back-to-back diode (35) wherein the diodes are isolated by a diode trench (6) having a depth at least equal to that of the epitaxial layer (24). A method of forming the interposer device is also provided. Figure
摘要翻译：插入器装置技术领域本发明涉及一种插入器装置，其包括在第一侧上具有外延层（24）的掺杂硅衬底（1）和从第一侧延伸到与第一侧相对的第二侧的通孔（11,12）掺杂硅衬底的第一侧。每个通孔包括由掺杂硅衬底的第一至第二侧延伸的周围沟槽（7）限定的掺杂硅衬底的体积，使得所述周围沟槽被布置为将由所述沟。第一和第二导电层（121,122）分别铺设在第一通孔的第一和第二侧上以便电连接在一起，并且第三和第四导电层（112,11）分别铺设在第二通孔以便电连接在一起。第一（122）和第三（112）导电层通过背对背二极管（35）连接在一起，其中二极管被二极管沟槽（6）隔离，二极管沟槽（6）的深度至少等于外延层（24）。还提供了一种形成插入器件的方法。数字

3. 发明申请

WO2015144755A1 CAPACITOR STRUCTURE 审中-公开
标题翻译：电容结构
公开(公告)号：WO2015144755A1
公开(公告)日：2015-10-01
申请号：PCT/EP2015/056380
申请日：2015-03-25
申请人： IPDIA
发明人： VOIRON, Frédéric , TENAILLEAU, Jean-René
IPC分类号： H01L23/64 , H01L29/66 , H01L25/065 , H01L25/07 , H01L49/02 , H01L23/522
CPC分类号： H01L28/91 , H01L25/074 , H01L28/65 , H01L28/75 , H01L29/66181 , H01L29/945 , H01L2224/16145
摘要： The invention relates to a capacitor structure (2) comprising a silicon substrate (4) with first and second sides (6, 8), a double double Metal Insulator Metal trench capacitor (10) including a basis electrode (12), an insulator layer (16, 20), a second and a third conductive layers (18, 22); and comprising a second pad (26) and a fourth pad (30) coupled to the basis electrode (12), a first pad (24) and a third pad (28) coupled together, the first pad (24) being located on the same substrate side than the second pad (26), the third pad (28) being located on the same substrate side than the fourth pad (30), the third pad (28) being coupled to the second conductive layer (18), said second conductive layer (18) being flush with or protruding from the opposite second side (8).
摘要翻译：本发明涉及一种包括具有第一和第二侧面（6,8）的硅衬底（4）的电容器结构（2），包括基极（12）的双重双金属绝缘体金属沟槽电容器（10），绝缘体层（16,20），第二和第三导电层（18,22）; 并且包括耦合到所述基础电极（12）的第二焊盘（26）和第四焊盘（30），耦合在一起的第一焊盘（24）和第三焊盘（28），所述第一焊盘（24）与第二垫（26）相同的衬底侧，第三衬垫（28）位于与第四衬垫（30）相同的衬底侧上，第三衬垫（28）与第二导电层（18）耦合，所述第二衬垫第二导电层（18）与相对的第二侧（8）齐平或突出。

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