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1. 发明申请

WO2011073940A1 DATA MANAGEMENT IN SOLID STATE STORAGE SYSTEMS 审中-公开
标题翻译：固态存储系统中的数据管理
公开(公告)号：WO2011073940A1
公开(公告)日：2011-06-23
申请号：PCT/IB2010/055875
申请日：2010-12-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu , ILIADIS, Ilias , MITTELHOLZER, Thomas
发明人： CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu , ILIADIS, Ilias , MITTELHOLZER, Thomas
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1012 , G06F11/1068 , G06F11/108
摘要： Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage (6) of a solid state storage system (5). Input data is stored in successive groups of data write locations in the solid state storage (6). Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage (6). The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords. The encoding and storage operation is performed such that, in each said group, the encoded input data comprises a plurality of first codewords in each of a plurality of the logical subdivisions and each logical subdivision contains a portion of each of the second codewords for that group.
摘要翻译：提供了用于控制数据管理操作的方法和装置，包括在固态存储系统（5）的固态存储（6）中存储数据。输入数据存储在固态存储器（6）中的连续的数据写入位置组中。每个组包括在固态存储器（6）的多个逻辑子部分中的每一个中的一组写入位置。要存储在每个组中的输入数据根据第一和第二线性纠错码进行编码。通过从输入数据中构成数据符号的行和列的逻辑阵列，来构成编码。行和列分别根据第一和第二线性纠错码编码以产生编码阵列，其中所有行对应于相应的第一码字和列对应于相应的第二码字。执行编码和存储操作，使得在每个所述组中，编码的输入数据包括多个逻辑子部分中的每一个中的多个第一码字，并且每个逻辑细分包含该组的每个第二码字的一部分。

2. 发明申请

WO2011073939A1 DATA MANAGEMENT IN SOLID STATE STORAGE DEVICES 审中-公开
标题翻译：固态存储设备中的数据管理
公开(公告)号：WO2011073939A1
公开(公告)日：2011-06-23
申请号：PCT/IB2010/055874
申请日：2010-12-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu , ILIADIS, Ilias
发明人： CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu , ILIADIS, Ilias
IPC分类号： G06F11/10
CPC分类号： G06F11/108 , G06F11/1008 , G06F11/1068 , H03M13/05
摘要： Methods and apparatus are provided for controlling a solid state storage device (5) in which the solid state storage (6) comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage (6). The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage (6), is maintained in memory (13). An indication of validity of data stored in each data write location is also maintained. Prior to erasing a block, valid input data is recovered from the or each said group containing write locations in that block. The recovered data is then re-stored as new input data.
摘要翻译：提供了用于控制固态存储设备（5）的方法和装置，其中固态存储器（6）包括每个包括多个数据写入位置的可擦除块。输入数据存储在连续的数据写入位置组中，每组包括在固态存储器（6）的多个逻辑子部分中的每一个中的一组可擦除块中的写入位置。输入数据被纠错编码，使得每个组包含用于该组中的输入数据的纠错码。指示固态存储器（6）中的输入数据的位置的元数据被保存在存储器（13）中。还保持了存储在每个数据写入位置中的数据的有效性的指示。在擦除块之前，从该块中包含写入位置的该组或每个所述组恢复有效的输入数据。然后将恢复的数据重新存储为新的输入数据。

3. 发明申请

WO2011064754A1 SOLID-STATE STORAGE SYSTEM WITH PARALLEL ACCESS OF MULTIPLE FLASH/PCM DEVICES 审中-公开
标题翻译：具有并行访问多个闪存/ PCM设备的固态存储系统
公开(公告)号：WO2011064754A1
公开(公告)日：2011-06-03
申请号：PCT/IB2010/055458
申请日：2010-11-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANTONAKOPOULOS, Theodore A. , CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu , ILIADIS, Ilias
发明人： ANTONAKOPOULOS, Theodore A. , CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu , ILIADIS, Ilias
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1028 , G11C29/765
摘要： Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.
摘要翻译：提供了通过使用容错架构以及用于随机/突发错误校正的一个纠错码（ECC）机制来解决固态驱动器（SSD）中的故障存储集成电路（IC）的问题的系统和方法，以及 L折叠交织机制。当一个或多个集成电路出现故障并且允许从故障集成电路恢复先前存储的数据并且允许在其他操作集成电路中校正随机/突发错误时，本文描述的系统和方法保持SSD的可操作性。这些系统和方法用作为备用集成电路处理的全功能/可操作集成电路来代替故障集成电路。此外，这些系统和方法在最大可实现的读/写数据速率方面提高了I / O性能。

4. 发明申请

WO2012001556A1 WEAR-LEVELING OF CELLS/PAGES/SUB-PAGES/BLOCKS OF A MEMORY 审中-公开
标题翻译：细胞/页/子页/记忆块的磨损等级
公开(公告)号：WO2012001556A1
公开(公告)日：2012-01-05
申请号：PCT/IB2011/052492
申请日：2011-06-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CIDECIYAN, Roy, Daron , ELEFTHERIOU, Evangelos, S. , HAAS, Robert , HU, Xiaoyu , ILIADIS, Ilias , PLETKA, Roman, A.
发明人： CIDECIYAN, Roy, Daron , ELEFTHERIOU, Evangelos, S. , HAAS, Robert , HU, Xiaoyu , ILIADIS, Ilias , PLETKA, Roman, A.
IPC分类号： G11C16/34
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C16/3495
摘要： The invention is directed to a method for wear-leveling cells or pages or sub- pages or blocks of a memory such as a flash memory, the method comprising: - receiving (S10) a chunk of data to be written on a cell or page or sub-page or block of the memory; - counting (S40) in the received chunk of data the number of times a given type of binary data '0' or Ί ' is to be written; and - distributing (S50) the writing of the received chunk of data amongst cells or pages or sub-pages or blocks of the memory such as to wear-level the memory with respect to the number of the given type of binary data '0' or Ί ' counted in the chunk of data to be written.
摘要翻译：本发明涉及一种用于对诸如闪速存储器之类的存储器的单元格或页面或子页面或块进行磨损均衡的方法，所述方法包括： - 接收（S10）要写入单元或页面的数据块或子页或块的存储器; - 在接收到的数据块中计数（S40）次数给定类型的二进制数据“0”或？ “要写以及 - 分配（S50）在存储器的单元格或页面或子页面或块之间写入所接收的数据块，以便相对于给定类型的二进制数据“0”的数量对存储器进行磨损级别要么？ “在数据块中计算要写入。

5. 发明申请

WO2011021126A1 DATA STORAGE SYSTEM AND METHOD FOR OPERATING A DATA STORAGE SYSTEM 审中-公开
标题翻译：用于操作数据存储系统的数据存储系统和方法
公开(公告)号：WO2011021126A1
公开(公告)日：2011-02-24
申请号：PCT/IB2010/053544
申请日：2010-08-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos, S , HAAS, Robert , HU, Xiaoyu , ILIADIS, Ilias
发明人： ELEFTHERIOU, Evangelos, S , HAAS, Robert , HU, Xiaoyu , ILIADIS, Ilias
IPC分类号： G06F3/06 , G06F12/02 , G11C16/34
CPC分类号： G06F3/0647 , G06F3/0616 , G06F3/0688 , G06F12/0246 , G06F2212/7208 , G06F2212/7211
摘要： A data storage system comprising at least one memory device array comprising memory devices for storing data; and a storage subsystem controller for performing a method for operating said memory devices within said memory device array by relocating parity entities from a first memory device to a spare memory device replacing a failed memory device, and by storing one or more of reconstructed data entities on the first memory device.
摘要翻译：一种数据存储系统，包括至少一个包括用于存储数据的存储器件的存储器件阵列; 以及存储子系统控制器，用于通过将奇偶校验实体从第一存储器设备重新定位到替换故障存储器设备的备用存储器设备，以及通过将一个或多个重构数据实体存储在其上来执行用于操作所述存储器设备阵列内的所述存储器设备的方法第一个存储设备。

6. 发明申请

WO2011070526A1 FLASH MEMORY CONTROLLER 审中-公开
标题翻译：闪存控制器
公开(公告)号：WO2011070526A1
公开(公告)日：2011-06-16
申请号：PCT/IB2010/055684
申请日：2010-12-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu
发明人： ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu
IPC分类号： G06F13/16
CPC分类号： G06F13/1668 , G06F9/3004 , G11C7/1042
摘要： A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps.
摘要翻译：闪存控制器通过第一闪存存储器接口耦合到第一闪存存储器封装，并通过第一闪存存储器接口耦合到第二闪存存储器封装。闪存控制器被设计为接收与第一闪存存储器包相关的第一指令，并且根据第一指令执行第一处理。闪存控制器还被设计为接收与第二闪存存储器包相关的第二指令，并且根据第二指令执行第二处理。闪存控制器还适用于将第一进程分成至少两个第一子步骤，并将第二进程分成至少两个第二子步骤。闪存控制器还适用于执行第一和第二子步骤，并且用于交错执行第一和第二子步骤。

7. 发明申请

WO2011151759A1 DECODING OF LDPC CODE 审中-公开
标题翻译： LDPC码的解码
公开(公告)号：WO2011151759A1
公开(公告)日：2011-12-08
申请号：PCT/IB2011/052268
申请日：2011-05-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiaoyu , NGUYEN, Dung Viet
发明人： ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiaoyu , NGUYEN, Dung Viet
IPC分类号： H03M13/11
CPC分类号： H03M13/1105 , H03M13/1108 , H03M13/2957
摘要： It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.
摘要翻译：提供了一种用于解码由LPDC码编码的比特序列的方法。该方法包括提供一组位状态，包括第一状态和第二状态，以及一组条件以改变包括第一条件5和第二状态的位状态。第一个条件和第二个条件是不同的。该方法包括读取序列的每个比特的值，根据读取的值将每个比特与组的相应状态相关联，确定满足评估条件并改变目标比特的状态作为结果条件得到满足然后，该方法可以根据其状态来设置10序列的目标比特的值。这种方法提供了一种解码方案，用于以比典型的比特翻转算法更好的性能来解码由LDPC码编码的比特序列，只有稍微增加的复杂度。

8. 发明申请

WO2011033450A1 CONTAINER MARKER SCHEME FOR REDUCING WRITE AMPLIFICATION IN SOLID STATE DEVICES 审中-公开
标题翻译：用于减少固体装置中的写入放大的集装箱标记方案
公开(公告)号：WO2011033450A1
公开(公告)日：2011-03-24
申请号：PCT/IB2010/054141
申请日：2010-09-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiaoyu
发明人： ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiaoyu
IPC分类号： G11C16/34
CPC分类号： G11C16/349 , G11C16/3495
摘要： A solid state storage device (300) and method are provided. Multiple blocks (310, 315) are configured as storage memory for a solid state storage device (300), and each block includes multiple pages. A controller (305) is configured to operate the solid state storage device (300). A free block (310) of the multiple blocks is assigned a marker level by the controller (305). For a particular page of the multiple pages, each particular page of data is written to a block (300) of the multiple blocks with a marker level corresponding to a level of dynamicity calculated by the controller (305) for that particular page.
摘要翻译：提供固态存储装置（300）和方法。多个块（310,315）被配置为用于固态存储设备（300）的存储存储器，并且每个块包括多个页面。控制器（305）被配置为操作固态存储设备（300）。多个块的空闲块（310）由控制器（305）分配标记级别。对于多页的特定页面，每个特定页面的数据被写入多个块的块（300），其中标记级别对应于由该特定页面的控制器（305）计算出的动态程度。

9. 发明申请

WO2011013054A1 WRITE-ERASE ENDURANCE LIFETIME OF MEMORY STORAGE DEVICES 审中-公开
标题翻译：内存存储设备的写保护寿命寿命
公开(公告)号：WO2011013054A1
公开(公告)日：2011-02-03
申请号：PCT/IB2010/053382
申请日：2010-07-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos S , HAAS, Robert , HU, Xiaoyu
发明人： ELEFTHERIOU, Evangelos S , HAAS, Robert , HU, Xiaoyu
IPC分类号： G06F12/02 , G11C16/34
CPC分类号： B62D35/001 , G06F12/0246 , G06F2212/1044 , G06F2212/7205 , G06F2212/7211 , G11C16/349 , G11C16/3495
摘要： A memory management system and method for managing memory blocks of a memory device of a computer. The system includes a free block data structure (12) including free memory blocks (14) for writing, and sorting the free memory blocks in a predetermined order based on block write-erase endurance cycle count and receiving new user-write requests to update existing data and relocation write requests to relocate existing data separately, a user-write block pool (IS) for receiving youngest blocks holding user-write data (i.e., any page being updated frequently) from the free block data structure, a relocation block pool (20) for receiving oldest blocks holding relocation data (i.e., any page being updated infrequently) from the free block data structure, and a garbage collection pool structure (24) for selecting at least one of user-write blocks and relocation blocks for garbage collection, wherein the selected block is moved back to the free block data structure upon being relocated and erased.
摘要翻译：一种用于管理计算机的存储器件的存储器块的存储器管理系统和方法。该系统包括一个空闲块数据结构（12），包括用于写入的空闲存储器块（14），并且基于块写擦除耐久循环计数以预定顺序对可用存储器块进行排序，并且接收新的用户写入请求以更新现有的数据和重新定位写请求以分别重新定位现有数据;用户接收块池（IS），用于从空闲块数据结构接收保存用户写入数据（即，任何被频繁更新的页面）的最小块， 20），用于从所述空闲块数据结构接收保持重定位数据（即，不经常更新的任何页面）的最旧块，以及用于选择用于垃圾收集的用户写入块和重定位块中的至少一个的垃圾收集池结构（24），其中所选择的块在重新定位和擦除时被移回到空闲块数据结构。

10. 发明申请

WO2011073902A1 REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS 审中-公开
标题翻译：在基于闪存的存储器系统中减少访问内容
公开(公告)号：WO2011073902A1
公开(公告)日：2011-06-23
申请号：PCT/IB2010/055802
申请日：2010-12-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos S. , HAAS, Robert , MUELLER, Peter , PLETKA, Roman A.
发明人： ELEFTHERIOU, Evangelos S. , HAAS, Robert , MUELLER, Peter , PLETKA, Roman A.
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.
摘要翻译：示例性实施例包括一种用于减少基于闪存的存储器系统中的访问争用的方法，该方法包括从具有多个信道的存储器件和多个存储器块中选择具有空闲状态的芯片条带，其中芯片条带包括多个页面，将所述条纹设置为写入状态，在所述闪存条带中的所述多个通道中的每一个上设置所述多个通道中的每一个中的写入队列头部，将写入队列头部设置到第一自由页面中属于来自芯片条带的信道的芯片，根据写入分配调度器在信道之间分配写请求，生成页写入，并响应于页写，增加写队列头，并将芯片条设置为on 线状态当它满了。

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