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1. 发明申请

WO2012001556A1 WEAR-LEVELING OF CELLS/PAGES/SUB-PAGES/BLOCKS OF A MEMORY 审中-公开
标题翻译：细胞/页/子页/记忆块的磨损等级
公开(公告)号：WO2012001556A1
公开(公告)日：2012-01-05
申请号：PCT/IB2011/052492
申请日：2011-06-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CIDECIYAN, Roy, Daron , ELEFTHERIOU, Evangelos, S. , HAAS, Robert , HU, Xiaoyu , ILIADIS, Ilias , PLETKA, Roman, A.
发明人： CIDECIYAN, Roy, Daron , ELEFTHERIOU, Evangelos, S. , HAAS, Robert , HU, Xiaoyu , ILIADIS, Ilias , PLETKA, Roman, A.
IPC分类号： G11C16/34
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C16/3495
摘要： The invention is directed to a method for wear-leveling cells or pages or sub- pages or blocks of a memory such as a flash memory, the method comprising: - receiving (S10) a chunk of data to be written on a cell or page or sub-page or block of the memory; - counting (S40) in the received chunk of data the number of times a given type of binary data '0' or Ί ' is to be written; and - distributing (S50) the writing of the received chunk of data amongst cells or pages or sub-pages or blocks of the memory such as to wear-level the memory with respect to the number of the given type of binary data '0' or Ί ' counted in the chunk of data to be written.
摘要翻译：本发明涉及一种用于对诸如闪速存储器之类的存储器的单元格或页面或子页面或块进行磨损均衡的方法，所述方法包括： - 接收（S10）要写入单元或页面的数据块或子页或块的存储器; - 在接收到的数据块中计数（S40）次数给定类型的二进制数据“0”或？ “要写以及 - 分配（S50）在存储器的单元格或页面或子页面或块之间写入所接收的数据块，以便相对于给定类型的二进制数据“0”的数量对存储器进行磨损级别要么？ “在数据块中计算要写入。

2. 发明申请

WO2011151759A1 DECODING OF LDPC CODE 审中-公开
标题翻译： LDPC码的解码
公开(公告)号：WO2011151759A1
公开(公告)日：2011-12-08
申请号：PCT/IB2011/052268
申请日：2011-05-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiaoyu , NGUYEN, Dung Viet
发明人： ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiaoyu , NGUYEN, Dung Viet
IPC分类号： H03M13/11
CPC分类号： H03M13/1105 , H03M13/1108 , H03M13/2957
摘要： It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.
摘要翻译：提供了一种用于解码由LPDC码编码的比特序列的方法。该方法包括提供一组位状态，包括第一状态和第二状态，以及一组条件以改变包括第一条件5和第二状态的位状态。第一个条件和第二个条件是不同的。该方法包括读取序列的每个比特的值，根据读取的值将每个比特与组的相应状态相关联，确定满足评估条件并改变目标比特的状态作为结果条件得到满足然后，该方法可以根据其状态来设置10序列的目标比特的值。这种方法提供了一种解码方案，用于以比典型的比特翻转算法更好的性能来解码由LDPC码编码的比特序列，只有稍微增加的复杂度。

3. 发明申请

WO2011121490A1 TWO -LEVEL BCH CODES FOR SOLID STATE STORAGE DEVICES 审中-公开
标题翻译：用于固态存储设备的两个BCH代码
公开(公告)号：WO2011121490A1
公开(公告)日：2011-10-06
申请号：PCT/IB2011/051219
申请日：2011-03-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , MITTELHOLZER, Thomas
发明人： CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , MITTELHOLZER, Thomas
IPC分类号： H03M13/15 , H03M13/29 , G06F11/10
CPC分类号： H03M13/2906 , G06F11/1072 , H03M13/152 , H03M13/2942
摘要： Methods and apparatus are provided for encoding input data for recording in s-level storage(2)of a solid state storage device(1), where s≥2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub- code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage(2).If each of the first and second codewords comprises N q-ary symbols where q =p k , k is a positive integer and p is a prime number, the q-ary code alphabet can be matched to the s-ary storage (2) by ensuring that q and s are u th and v th powers respectively of a common base r, where u and v are positive integers and k≥u, whereby p (k/u)v = s.
摘要翻译：提供了用于编码用于在固态存储装置（1）的s级存储器（2）中记录的输入数据的方法和装置，其中s = 2。输入数据字根据第一和第二BCH码以M个输入数据字的组进行编码，以针对每个组产生第一BCH码的一组M个第一码字。产生M个第一码字集合，使得M个第一码字的至少一个预定线性组合产生第二BCH码的第二码字，该第二BCH码是第一BCH码的子码。这些M个第一码字的集合然后被记录在s级存储器（2）中。如果第一和第二码字中的每一个包括N个q个符号，其中q = pk，k是正整数，p是素数，通过确保q和s分别是公共基础r的uth和vth功率，其中u和v是正整数，并且k = u，可以将q元代码字母表与s存储器（2）匹配，由此p （k / u）v = s。

4. 发明申请

WO2009136374A2 HEAD DESIGN FOR WRITING SERVO PATTERNS ON MAGNETIC TAPE 审中-公开
标题翻译：用于在磁带上书写伺服图案的头设计
公开(公告)号：WO2009136374A2
公开(公告)日：2009-11-12
申请号：PCT/IB2009/051882
申请日：2009-05-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHERUBINI, Giovanni , CIDECIYAN, Roy, D. , ELEFTHERIOU, Evangelos, S. , JELITTO, Jens , LANTZ, Mark, A.
发明人： CHERUBINI, Giovanni , CIDECIYAN, Roy, D. , ELEFTHERIOU, Evangelos, S. , JELITTO, Jens , LANTZ, Mark, A.
IPC分类号： G11B5/584 , G11B21/10
CPC分类号： G11B5/584
摘要： A servo write head is provided and is configured to simultaneously write at least two servo patterns in respective servo bands on linear magnetic tape. Centerlines of the servo patterns are substantially uniformly spaced in the lateral direction. In addition, the servo patterns of all adjacent respective servo bands are displaced relative to each other in a longitudinal direction by an amount that is related to a length of a servo frame and a type of the servo patterns.
摘要翻译：提供了伺服写入头，并被配置为在线性磁带上的相应伺服带中同时写入至少两个伺服模式。伺服图案的中心线在横向方向上基本上均匀间隔开。此外，所有相邻的各个伺服带的伺服模式在纵向方向上相对于伺服帧的长度和伺服模式的类型相关的量而移位。

5. 发明申请

WO2008059406A1 OVERSAMPLED CHANNEL RESPONSE IDENTIFICATION 审中-公开
标题翻译：超声波通道响应识别
公开(公告)号：WO2008059406A1
公开(公告)日：2008-05-22
申请号：PCT/IB2007/054535
申请日：2007-11-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHERUBINI, Giovanni , ELEFTHERIOU, Evangelos, S. , HUTCHINS, Robert, Allen , JAQUETTE, Glen, Alan , OELCER, Sedat
发明人： CHERUBINI, Giovanni , ELEFTHERIOU, Evangelos, S. , HUTCHINS, Robert, Allen , JAQUETTE, Glen, Alan , OELCER, Sedat
IPC分类号： G11B20/10 , H04L25/03
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10212 , H04B1/7085 , H04J2013/0037 , H04L25/0212 , H04L25/03038
摘要： Methods, apparatus and computer programs are provided for multiplication-free identification of the impulse response of an oversampled data channel (3). An input ( a ) comprising a pseudo-random binary sequence of L symbols is supplied to the channel (3) at a symbol rate of 1/T. A channel output ( z ) is produced by sampling a channel output signal corresponding to the input (a) with a sampling interval T s = (q/p)T, where q and p are relative prime integers with q P(j)) are produced from the channel output ( z ) by selecting, for each polyphase sequence ( P(j)) , every p th sample of the channel output ( z ), with a phase shift of one sample between successive polyphase sequences ( p(j) ). A decimated binary sequence ( b ) is produced by selecting every q th symbol of the channel input ( a ). Each polyphase sequence ( p(j) ) is correlated with the decimated binary sequence ( b ), the two possible binary values being of equal magnitude and opposite sign for the correlation. The correlation results are accumulated to produce a correlated output sequence ( c(j) ) for that polyphase sequence (p(j) ). The samples of the correlated output sequences ( c(j) ) are then interleaved in phase order of the corresponding polyphase sequences ( p(j) ) to produce the impulse response of the channel.
摘要翻译：提供了方法，装置和计算机程序，用于对过采样数据信道（3）的脉冲响应进行无乘法识别。包含L个符号的伪随机二进制序列的输入（a）以符号率1 / T提供给信道（3）。通过以采样间隔T（t / p）T对与输入（a）相对应的通道输出信号进行采样来产生通道输出（z），其中q和p是相对第一整数对于q 个符号来产生抽取的二进制序列（b）。每个多相序列（p（j））与抽取的二进制序列（b）相关，两个可能的二进制值相等，相关的符号相反。累积相关结果以产生该多相序列（p（j））的相关输出序列（c（j））。然后，相关输出序列（c（j））的样本以对应的多相序列（p（j））的相位顺序进行交织，以产生信道的脉冲响应。

6. 发明申请

WO2004107338A1 DATA STORAGE SYSTEMS 审中-公开
标题翻译：数据存储系统
公开(公告)号：WO2004107338A1
公开(公告)日：2004-12-09
申请号：PCT/IB2004/001532
申请日：2004-05-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CIDECIYAN, Roy, D. , DHOLAKIA, Ajay , ELEFTHERIOU, Evangelos, S. , MITTELHOLZER, Thomas
发明人： CIDECIYAN, Roy, D. , DHOLAKIA, Ajay , ELEFTHERIOU, Evangelos, S. , MITTELHOLZER, Thomas
IPC分类号： G11B20/10
CPC分类号： G11B20/1833
摘要： Described is a method and apparatus for decoding data in a data storage system. In operation, a detector generates an output bit stream in dependence on a data block received from a storage subsystem of the data storage system. A post processor connected to the detector generates a first error corrected bit stream in dependence on the output bit stream and the data block. An error correction decoder connected to the post processor generates a second error corrected bit stream in dependence on the first error corrected bit stream and also generates a checksum in dependence of the second error corrected bit stream. A feedback path supplies from the error correction decoder to the post processor pinning data indicative of locations of correct bits in the second error corrected bit stream in the event that the checksum is indicative of errors in the second error corrected bit stream and the second error corrected bit stream comprises at least one correct interleave. The post processor regenerates the first error corrected bit stream in dependence on the pinning data received from the error correction decoder.
摘要翻译：描述了一种用于对数据存储系统中的数据进行解码的方法和装置。在操作中，检测器根据从数据存储系统的存储子系统接收的数据块产生输出位流。连接到检测器的后处理器根据输出比特流和数据块生成第一纠错比特流。连接到后处理器的纠错解码器根据第一纠错比特流产生第二纠错比特流，并且还根据第二纠错比特流产生校验和。在校验和指示第二纠错比特流中的错误并且校正的第二错误的情况下，反馈路径从错误校正解码器向后处理器提供钉扎指示第二纠错比特流中的正确比特的位置的数据位流包括至少一个正确的交错。后处理器根据从纠错解码器接收的钉扎数据重新生成第一纠错比特流。

7. 发明申请

WO2012029007A1 CELL-STATE DETERMINATION IN PHASE-CHANGE MEMORY 审中-公开
标题翻译：相变记忆中的细胞状态测定
公开(公告)号：WO2012029007A1
公开(公告)日：2012-03-08
申请号：PCT/IB2011/053757
申请日：2011-08-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos S. , PANTAZI, Angeliki , PAPANDREOU, Nikolaos , POZIDIS, Charalampos , SEBASTIAN, Abu
发明人： ELEFTHERIOU, Evangelos S. , PANTAZI, Angeliki , PAPANDREOU, Nikolaos , POZIDIS, Charalampos , SEBASTIAN, Abu
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C7/1006 , G11C11/5678 , G11C13/004
摘要： Methods and apparatus are provided for determining the state of a phase-change memory cell. A plurality of measurements are made on the cell, the measurements being dependent on the sub-threshold current-versus-voltage characteristic of the cell. The measurements are processed to obtain a metric which is dependent on the slope of the sub- threshold current-versus-voltage characteristic. The state of the cell is then determined in dependence on this metric which, unlike absolute cell resistance,is substantially unaffected by drift.
摘要翻译：提供了用于确定相变存储器单元的状态的方法和装置。对单元进行多个测量，测量取决于单元的次阈值电流对电压特性。处理测量以获得取决于子阈值电流对电压特性的斜率的度量。然后根据该度量确定单元的状态，其与绝对单元电阻不同，基本上不受漂移的影响。

8. 发明申请

WO2011121491A1 PROGRAMMING AT LEAST ONE MULTI-LEVEL PHASE CHANGE MEMORY CELL 审中-公开
标题翻译：编程至少一个多级相变记忆细胞
公开(公告)号：WO2011121491A1
公开(公告)日：2011-10-06
申请号：PCT/IB2011/051220
申请日：2011-03-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos S. , PANTAZI, Angeliki , PAPANDREOU, Nikolaos , POZIDIS, Charalampos , SEBASTIAN, Abu
发明人： ELEFTHERIOU, Evangelos S. , PANTAZI, Angeliki , PAPANDREOU, Nikolaos , POZIDIS, Charalampos , SEBASTIAN, Abu
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0097 , G11C2013/0078
摘要： A method is provided that comprises a step of programming the PCM cell to have a respective definite cell state by at least one current pulse flowing to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level, a step of controlling said respective current pulse by a respective bitline pulse and a respective wordline pulse, and a step of controlling said respective bitline pulse and said respective wordline pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level.
摘要翻译：提供了一种方法，其包括通过流向PCM单元的至少一个电流脉冲对PCM单元进行编程以具有相应的确定单元状态的步骤，所述相应的确定单元状态至少由相应的确定电阻水平限定，步骤通过相应的位线脉冲和相应的字线脉冲来控制所述各个电流脉冲，以及根据PCM单元的实际电阻值来控制所述各个位线脉冲和所述各个字线脉冲的步骤，以及相应的参考电阻值被定义为确定阻力位。

9. 发明申请

WO2011092642A1 METHOD AND APPARATUS FOR OPERATING A STORAGE DEVICE 审中-公开
标题翻译：用于操作存储设备的方法和装置
公开(公告)号：WO2011092642A1
公开(公告)日：2011-08-04
申请号：PCT/IB2011/050356
申请日：2011-01-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELEFTHERIOU, Evangelos S. , HAEBERLE, Walter , JELITTO, Jens , PANTAZI, Angeliki
发明人： ELEFTHERIOU, Evangelos S. , HAEBERLE, Walter , JELITTO, Jens , PANTAZI, Angeliki
IPC分类号： G11B5/584
CPC分类号： G11B5/584
摘要： Method for operating a storage device with a tape (TP) and a head (HU) wherein the head (HU) comprises a first and a second read element (RE1, RE2). Each read element (RE1, RE2) is operable to detect servo-pattern of a particular servo band (SP). The first and the second read element (RE1, RE2) are arranged in such a way, that the tape (TP) at first passes one of both read elements (RE1, RE2) and subsequently passes the other of both read elements (RE1, RE2) when the tape (TP) moves in a predetermined longitudinal direction (X). A tape transport direction (TPDIR) of the tape (TP) along the longitudinal direction (X) is determined. The first read element (RE1) is selected dependent on the determined tape transport direction (TPDIR), when the determined tape transport direction (TPDIR) represents a direction where the tape (TP) at first passes the first read element (RE1) and subsequently the second read element (RE2). Otherwise the second read element (RE2) is selected. A position error signal (PES1) is determined dependent on the selected read element. With respect to a predetermined lateral reference point (REF) an estimated lateral track position ( d est ) at a longitudinal position (x1) of the selected read element is estimated dependent on the determined position error signal (PES1). With respect to the predetermined reference point (REF) another estimated lateral track position ( d* est ) at a longitudinal position (x2) of the non- selected read element is estimated in such a way that the other estimated lateral track position ( d* est ) becomes a time-delayed representation of the estimated lateral track position ( d est ).
摘要翻译：用于使用带（TP）和头（HU）操作存储设备的方法，其中所述头部（HU）包括第一和第二读取元件（RE1，RE2）。每个读取元件（RE1，RE2）可用于检测特定伺服带（SP）的伺服模式。第一和第二读取元件（RE1，RE2）以这样的方式排列，即带（TP）首先通过两个读取元件（RE1，RE2）中的一个，然后将两个读取元件（RE1，当胶带（TP）在预定的纵向方向（X）移动时，RE2）。确定带（TP）沿着纵向（X）的带传送方向（TPDIR）。当确定的磁带传输方向（TPDIR）表示磁带（TP）首先通过第一读取单元（RE1）并且随后的传输方向（TPDIR））时，第一读取单元（RE1）被选择，取决于确定的磁带传输方向（TPDIR）第二个读取元素（RE2）。否则选择第二个读取元素（RE2）。取决于所选择的读取元素来确定位置误差信号（PES1）。相对于预定的横向参考点（REF），所选择的读取元件的纵向位置（x1）处的估计横向轨迹位置（d est）取决于所确定的位置误差信号（PES1）来估计。对于预定的参考点（REF），以非选择的读取元件的纵向位置（x2）处的另一个估计横向轨迹位置（d * est）被估计为使得另一个估计的横向轨道位置（d * est）成为估计侧向轨道位置（d est）的时间延迟表示。

10. 发明申请

WO2011073940A1 DATA MANAGEMENT IN SOLID STATE STORAGE SYSTEMS 审中-公开
标题翻译：固态存储系统中的数据管理
公开(公告)号：WO2011073940A1
公开(公告)日：2011-06-23
申请号：PCT/IB2010/055875
申请日：2010-12-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu , ILIADIS, Ilias , MITTELHOLZER, Thomas
发明人： CIDECIYAN, Roy D. , ELEFTHERIOU, Evangelos S. , HAAS, Robert , HU, Xiao-Yu , ILIADIS, Ilias , MITTELHOLZER, Thomas
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1012 , G06F11/1068 , G06F11/108
摘要： Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage (6) of a solid state storage system (5). Input data is stored in successive groups of data write locations in the solid state storage (6). Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage (6). The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords. The encoding and storage operation is performed such that, in each said group, the encoded input data comprises a plurality of first codewords in each of a plurality of the logical subdivisions and each logical subdivision contains a portion of each of the second codewords for that group.
摘要翻译：提供了用于控制数据管理操作的方法和装置，包括在固态存储系统（5）的固态存储（6）中存储数据。输入数据存储在固态存储器（6）中的连续的数据写入位置组中。每个组包括在固态存储器（6）的多个逻辑子部分中的每一个中的一组写入位置。要存储在每个组中的输入数据根据第一和第二线性纠错码进行编码。通过从输入数据中构成数据符号的行和列的逻辑阵列，来构成编码。行和列分别根据第一和第二线性纠错码编码以产生编码阵列，其中所有行对应于相应的第一码字和列对应于相应的第二码字。执行编码和存储操作，使得在每个所述组中，编码的输入数据包括多个逻辑子部分中的每一个中的多个第一码字，并且每个逻辑细分包含该组的每个第二码字的一部分。

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