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1. 发明申请

WO2011149587A1 INTEGRATED CIRCUIT WITH FINFETS AND MIM FIN CAPACITOR 审中-公开
标题翻译：集成电路与FINFET和MIM FIN电容
公开(公告)号：WO2011149587A1
公开(公告)日：2011-12-01
申请号：PCT/US2011/030675
申请日：2011-03-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BOOTH, Roger, A. , KANGGUO, Cheng , FURUKAWA, Toshiharu , PEI, Chengwen
发明人： BOOTH, Roger, A. , KANGGUO, Cheng , FURUKAWA, Toshiharu , PEI, Chengwen
IPC分类号： H01L27/06 , H01L21/336 , H01L29/94 , H01L29/78 , H01L21/8238 , H01L21/84 , H01L27/12
CPC分类号： H01L27/0629 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/845 , H01L27/1211 , H01L28/91
摘要： An integrated circuit having finFETs(60a,b) and a metal-insulator-metal (MIM) fin capacitor (65) and methods of manufacture are disclosed. A method includes forming a first finFET (60a) comprising a first dielectric (25) and a first conductor (30); forming a second finFET (60b) comprising a second dielectric (40) and a second conductor (45); and forming a fin capacitor (65) comprising the first conductor (25), the second dielectric (40), and the second conductor (45).
摘要翻译：公开了一种具有finFET（60a，b）和金属 - 绝缘体 - 金属（MIM）鳍式电容器（65）的集成电路及其制造方法。一种方法包括形成包括第一电介质（25）和第一导体（30）的第一finFET（60a）; 形成包括第二电介质（40）和第二导体（45）的第二finFET（60b）; 以及形成包括所述第一导体（25），所述第二电介质（40）和所述第二导体（45）的散热片电容器（65）。

2. 发明申请

WO2011139872A1 ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM 审中-公开
标题翻译： EDRAM的增强电容深度电容器
公开(公告)号：WO2011139872A1
公开(公告)日：2011-11-10
申请号：PCT/US2011/034430
申请日：2011-04-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , KWON, Oh-Jung , LEE, Junedong , PEI, Chengwen , WANG, Geng
发明人： KWON, Oh-Jung , LEE, Junedong , PEI, Chengwen , WANG, Geng
IPC分类号： H01L29/94
CPC分类号： H01L28/82 , H01L27/10867 , H01L29/66181
摘要： A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.
摘要翻译：提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。可以形成存取晶体管和其它逻辑器件。

3. 发明申请

WO2013019305A1 EPITAXIAL EXTENSION CMOS TRANSISTOR 审中-公开
标题翻译：外延扩展CMOS晶体管
公开(公告)号：WO2013019305A1
公开(公告)日：2013-02-07
申请号：PCT/US2012/040067
申请日：2012-05-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , PEI, Chengwen , WANG, Geng , ZHANG, Yanli
发明人： PEI, Chengwen , WANG, Geng , ZHANG, Yanli
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth d 1 around a gate structure on the semiconductor layer, forming a disposable spacer 58 around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth d2 greater than the first depth d1. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region 16 and an integrated epitaxial drain and drain extension region 18. A replacement gate structure can be formed after deposition and of a planarization dielectric layer 70 and subsequent removal of the gate structure and laterally expand the gate cavity 59 over expitaxial source 16 and drain extension regions 18. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.
摘要翻译：通过在半导体层上形成围绕栅极结构的第一深度d 1的一对第一沟槽，在半导体层中形成一对水平台阶包含的沟槽，在栅极结构周围形成一次性间隔件58以覆盖近端部分并且通过形成大于第一深度d1的第二深度d2的一对第二沟槽。去除一次性间隔物，并且进行选择性外延以形成集成的外延源和源极延伸区域16以及集成的外延漏极和漏极扩展区域18.可以在沉积之后形成替代栅极结构，并且可以在平坦化介电层70和随后去除栅极结构并且在外延源极16和漏极延伸区域18上横向膨胀栅极腔59.或者，可以将接触电介质层直接沉积在集成的外延区上，并且可以在其中形成接触通孔结构。

4. 发明申请

WO2010081616A1 SPACER AND GATE DIELECTRIC STRUCTURE FOR PROGRAMMABLE HIGH-K/METAL GATE MEMORY TRANSISTORS INTEGRATED WITH LOGIC TRANSISTORS AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：与逻辑晶体管集成的可编程高K /金属栅极存储晶体管的间隔栅极电介质结构及其形成方法
公开(公告)号：WO2010081616A1
公开(公告)日：2010-07-22
申请号：PCT/EP2009/067671
申请日：2009-12-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , BOOTH, Roger, Allen, Jr , KOTHANDARAMAN, Chandrasekara , CHENG, Kangguo , PEI, Chengwen
发明人： BOOTH, Roger, Allen, Jr , KOTHANDARAMAN, Chandrasekara , CHENG, Kangguo , PEI, Chengwen
IPC分类号： H01L21/28 , H01L21/336 , H01L29/792 , H01L27/115 , H01L21/8234 , H01L29/51 , H01L29/423 , H01L29/49 , H01L21/8247 , H01L21/8239
CPC分类号： H01L29/78 , H01L21/28282 , H01L21/823462 , H01L21/823468 , H01L27/1052 , H01L27/11573 , H01L29/4234 , H01L29/4983 , H01L29/517 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack overlying a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode (16) and a second metal gate electrode (21) on the semiconductor substrate. In a next process sequence, at least one spacer (55) is formed on the first metal gate electrode overlying a portion of the high-k gate dielectric layer, (12) wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric (17) having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric (22) having an edge that is aligned to a sidewall of the second metal gate electrode. Electrons can be trapped in the spacer (55).
摘要翻译：提供了一种制造存储器件的方法，其可以开始形成覆盖在半导体衬底上的分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅极电极 16）和第二金属栅电极（21）。在下一个处理顺序中，在覆盖高k栅极电介质层的一部分的第一金属栅电极上形成至少一个间隔物（55）（12），其中暴露高k栅极电介质的剩余部分。蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质（17）和第二高k栅极电介质（22），具有与第二金属栅电极的侧壁对准的边缘。电子可以被捕获在间隔物（55）中。

5. 发明申请

WO2015043419A1 RECONFIGURABLE MULTI-STACK INDUCTOR 审中-公开
标题翻译：可重构多层电感器
公开(公告)号：WO2015043419A1
公开(公告)日：2015-04-02
申请号：PCT/CN2014/086876
申请日：2014-09-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) CO., LIMITED
发明人： SUN, Pingping , PEI, Chengwen , XU, Zheng
IPC分类号： H01F21/12 , H01L23/64
CPC分类号： H01F27/362 , H01F17/0013 , H01F27/2804 , H01F27/2871 , H01F27/289 , H01F41/041 , H01F2017/008 , H01F2027/2809 , H01L23/60 , H01L23/645 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
摘要： A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure. A second ground shielding structure located within the second metal layer is electrically isolated from and circumferentially bounds the second inductor structure, whereby the first and second inductor generate a first inductance value based on the first ground shielding structure and second ground shielding structure being coupled to ground, and the first and second inductor generate a second inductance value based on the first ground shielding structure and second ground shielding structure electrically floating.
摘要翻译：形成在半导体结构内的可重构多叠层电感器可以包括位于半导体结构的第一金属层内的第一电感结构，位于第一金属层内的第一接地屏蔽结构，其与第一电感器结构，以及位于半导体结构的第二金属层内的第二电感结构，由此第二电感结构电耦合到第一电感结构。位于第二金属层内的第二接地屏蔽结构与第二电感器结构电隔离并在周向上限定第二电感结构，由此第一和第二电感器基于第一接地屏蔽结构产生第一电感值，并且第二接地屏蔽结构耦合到地并且第一和第二电感器基于第一接地屏蔽结构和电浮置的第二接地屏蔽结构产生第二电感值。

6. 发明申请

WO2016132275A1 ON-CHIP SEMICONDUCTOR DEVICE HAVING ENHANCED VARIABILITY 审中-公开
标题翻译：具有增强可变性的片上半导体器件
公开(公告)号：WO2016132275A1
公开(公告)日：2016-08-25
申请号：PCT/IB2016/050796
申请日：2016-02-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： WANG, Ping-Chuan , PEI, Chengwen , LI, Wai-Kin
IPC分类号： H01L29/78 , H01L21/82
CPC分类号： H01L23/576 , H01L21/28158 , H01L21/823462 , H01L23/573 , H01L27/0207 , H01L27/088 , H01L29/42368 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A physical unclonable function (PUF) semiconductor device (100) includes a semiconductor substrate extending along a first direction to define a length and a second direction opposite the first direction to define a thickness. At least one pair of semiconductor structures (102a, 102b) is formed on the semiconductor substrate. The semiconductor structures (102a, 102b) include a first semiconductor structure (102a) and a second semiconductor structure (102b). The first semiconductor structure (102a) includes a first gate dielectric layer (120a) having a first shape that defines a first threshold voltage. The second semiconductor structure (102b) includes a second gate dielectric layer (120b) having a second dielectric shape that is reversely arranged with respect to the first shape and that defines a second threshold voltage different from the first threshold voltage.
摘要翻译：物理不可克隆功能（PUF）半导体器件（100）包括沿着第一方向延伸以限定长度的半导体衬底和与第一方向相反的第二方向以限定厚度。至少一对半导体结构（102a，102b）形成在半导体衬底上。半导体结构（102a，102b）包括第一半导体结构（102a）和第二半导体结构（102b）。第一半导体结构（102a）包括具有限定第一阈值电压的第一形状的第一栅介质层（120a）。第二半导体结构（102b）包括第二栅极电介质层（120b），其具有相对于第一形状相反地布置并且限定与第一阈值电压不同的第二阈值电压的第二电介质形状。

7. 发明申请

WO2014078045A1 SEMICONDUCTOR DEVICE HAVING DIFFUSION BARRIER TO REDUCE BACK CHANNEL LEAKAGE 审中-公开
标题翻译：具有扩散障碍物的半导体器件减少后向通道泄漏
公开(公告)号：WO2014078045A1
公开(公告)日：2014-05-22
申请号：PCT/US2013/066526
申请日：2013-10-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： FREEMAN, Gregory, G. , LEE, Kam-Leung , PEI, Chengwen , WANG, Geng , ZHANG, Yanli
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/26586 , H01L21/3247 , H01L21/76243 , H01L27/1087 , H01L27/10873 , H01L27/1203 , H01L29/0623 , H01L29/66181 , H01L29/78 , H01L29/78603 , H01L29/78612 , H01L29/78687 , H01L29/78696
摘要： A semiconductor-on-insulator (100) (SOI) substrate comprises a bulk semiconductor substrate (102), a buried insulator layer (106) formed on the bulk substrate (102) and an active semiconductor layer (104) formed on the buried insulator layer (106). Impurities (108) are implanted near the interface of the buried insulator layer (106) and the active semiconductor layer (104). A diffusion barrier layer (110) is formed between the impurities (108) and an upper surface of the active semiconductor layer (114). The diffusion barrier layer (110) prevents the impurities (108) from diffusing therethrough.
摘要翻译：绝缘体上半导体（100）（SOI）衬底包括体半导体衬底（102），形成在本体衬底（102）上的掩埋绝缘体层（106）和形成在掩埋绝缘体上的有源半导体层（104）层（106）。杂质（108）注入到埋入绝缘体层（106）和有源半导体层（104）的界面附近。在杂质（108）和有源半导体层（114）的上表面之间形成扩散阻挡层（110）。扩散阻挡层（110）防止杂质（108）扩散通过。

8. 发明申请

WO2013089953A1 RARE-EARTH OXIDE ISOLATED SEMICONDUCTOR FIN 审中-公开
标题翻译：稀土氧化物分离半导体FIN
公开(公告)号：WO2013089953A1
公开(公告)日：2013-06-20
申请号：PCT/US2012/064600
申请日：2012-11-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： CHENG, Kangguo , ERVIN, Joseph , PEI, Chengwen , TODI, Ravi, M. , WANG, Geng
IPC分类号： H01L21/336
CPC分类号： H01L21/02488 , H01L21/02513 , H01L21/02587 , H01L21/02598 , H01L21/02642 , H01L29/66795 , H01L29/785
摘要： A dielectric template layer is deposited on a substrate. Line trenches are formed within the dielectric template layer by an anisotropic etch that employs a patterned mask layer. The patterned mask layer can be a patterned photoresist layer, or a patterned hard mask layer that is formed by other image transfer methods. A lower portion of each line trench is filled with an epitaxial rare-earth oxide material by a selective rare-earth oxide epitaxy process. An upper portion of each line trench is filled with an epitaxial semiconductor material by a selective semiconductor epitaxy process. The dielectric template layer is recessed to form a dielectric material layer that provides lateral electrical isolation among fin structures, each of which includes a stack of a rare-earth oxide fin portion and a semiconductor fin portion.
摘要翻译：电介质模板层沉积在衬底上。通过使用图案化掩模层的各向异性蚀刻，在电介质模板层内形成线沟槽。图案化掩模层可以是图案化的光致抗蚀剂层，或者通过其它图像转印方法形成的图案化的硬掩模层。通过选择性稀土氧化物外延法，用外延稀土氧化物材料填充每个线沟槽的下部。通过选择性半导体外延工艺，用外延半导体材料填充每个线沟槽的上部。电介质模板层被凹入以形成介电材料层，该电介质材料层在散热片结构之间提供横向电隔离，其中每一个包括稀土氧化物翅片部分和半导体散热片部分的堆叠。

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