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1. 发明申请

WO2005071871A1 CLOCK RECOVERY METHODS AND APPARATUS 审中-公开
标题翻译：时钟恢复方法和装置
公开(公告)号：WO2005071871A1
公开(公告)日：2005-08-04
申请号：PCT/US2005/000867
申请日：2005-01-12
申请人： INTEL CORPORATION , STEPHENS, Adrian, P. , LOUKIANOV, Dmitrii
发明人： STEPHENS, Adrian, P. , LOUKIANOV, Dmitrii
IPC分类号： H04J3/06
CPC分类号： H04B7/269
摘要： A source application executed within a source device may packetize and send source data over a link to a destination application executed within a destination device. In various embodiments, clock recovery processes are performed in conjunction with the destination application in order to synchronize the rates of source data production and consumption (e.g., playback). To facilitate the clock recovery process, a transport delay is calculated based on the difference between a source MAC-layer timestamp and a destination MAC-layer timestamp that envelop portions of the link that include variable delay elements. The transport delay is used by the clock recovery process to adjust a source application-layer timestamp, in one embodiment. In another embodiment, the transport delay is used by the destination device to impart a fixed cumulative transport delay on the source data before it is delivered to the destination application.
摘要翻译：在源设备中执行的源应用可以通过链路将源数据分组化并发送到目的地设备内执行的目的地应用。在各种实施例中，时钟恢复过程与目的地应用一起执行，以便同步源数据生成和消耗（例如，回放）的速率。为了便于时钟恢复过程，基于包含可变延迟元素的链路的部分的源MAC层时间戳和目的MAC层时间戳之间的差异来计算传输延迟。在一个实施例中，时钟恢复过程使用传输延迟来调整源应用层时间戳。在另一个实施例中，目的地设备使用传输延迟来在源数据被传递到目的地应用之前对源数据赋予固定的累积传输延迟。

2. 发明申请

WO2013122613A1 METHOD, APPARATUS AND SYSTEM OF TRANSFERRING DATA BETWEEN ELEMENTS OF A CABLE COMMUNICATION DEVICE 审中-公开
标题翻译：方法，传输电缆通信设备元件数据的装置和系统
公开(公告)号：WO2013122613A1
公开(公告)日：2013-08-22
申请号：PCT/US2012/031038
申请日：2012-03-28
申请人： INTEL CORPORATION , SHULMAN, Shaul , LOUKIANOV, Dmitrii , GOLDMAN, Naor , ARAMBEPOLA, Bernard
发明人： SHULMAN, Shaul , LOUKIANOV, Dmitrii , GOLDMAN, Naor , ARAMBEPOLA, Bernard
IPC分类号： H04L29/12 , H04L29/10 , H04L27/00
CPC分类号： H04L5/14 , H04L1/0041 , H04L1/0083 , H04L12/2801 , H04L27/0002 , H04M11/00 , H04N21/6118 , H04N21/6168
摘要： Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.
摘要翻译：一些演示实施例包括在通信设备的元件之间传送信息的设备，系统和方法。例如，设备可以包括前端以接收包括多个下游数据信道的模拟下游输入，并且提供数字串行下游输出，其包括至少一个恒定尺寸的下游帧的连续流，包括多个常数确定下游数据帧，其包括所述多个下游数据信道的下游采样数据; 串行接口，包括至少一个串行通道，用于传输数字串行下游输出的至少上游; 以及处理器，通过串行接口接收数字串行下游，并处理下游数据帧。

3. 发明申请

WO2005017724A2 EVENT TIME-STAMPING 审中-公开
标题翻译：活动时间戳
公开(公告)号：WO2005017724A2
公开(公告)日：2005-02-24
申请号：PCT/US2004/024055
申请日：2004-07-28
申请人： INTEL CORPORATION , LOUKIANOV, Dmitrii
发明人： LOUKIANOV, Dmitrii
IPC分类号： G06F1/04
CPC分类号： G06F1/14
摘要： Machine-readable media, methods, and apparatus that time stamp events. In one embodiment, a time-stamping circuit may detect events of interest such as interrupt signals, arbitration signals, etc. In response to detecting such an event, the time-stamping circuit may store a time stamp for the event. A requester such as a processor may later request the time-stamping circuit for the time stamp of the event. The requester may then adjust a processing rate associated with the generation of such events based upon the retrieved time stamps.
摘要翻译：时间戳事件的机器可读介质，方法和装置。在一个实施例中，时间戳电路可以检测感兴趣的事件，例如中断信号，仲裁信号等。响应于检测到这种事件，时间戳电路可以存储事件的时间戳。诸如处理器的请求者可以稍后请求时间戳电路用于事件的时间戳。然后，请求者可以基于检索到的时间戳来调整与这种事件的生成相关联的处理速率。

4. 发明申请

WO2012115708A1 A SYSTEM, METHOD, AND DEVICE TO DISTRIBUTE ACCURATE SYNCHRONIZATION TIMESTAMPS IN AN EXPANDABLE AND TIMING CRITICAL SYSTEM 审中-公开
标题翻译：在可扩展和时序关键系统中分配精确同步时序的系统，方法和设备
公开(公告)号：WO2012115708A1
公开(公告)日：2012-08-30
申请号：PCT/US2011/067603
申请日：2011-12-28
申请人： INTEL CORPORATION , LOUKIANOV, Dmitrii
发明人： LOUKIANOV, Dmitrii
IPC分类号： G06F1/04 , G06F13/38
CPC分类号： H04J3/0697 , G06F1/14
摘要： Techniques are described to provide a device and network of devices that collect distributed coordinated timestamps from distributed time counters in a multi-module or multi-integrated circuit system. The interconnect between the modules can be a single-wire or a two-wire interconnect. The modules communicatively coupled to the interconnect can use a collision-avoidance protocol for triggering the broadcasting of timestamps among the modules as well for allowing all modules to transmit their timestamps. Timestamps from multiple clocks can be transmitted by all modules and then collected and compared to produce correction factors to clock signals of each module to potentially achieve distributed clock synchronization in multiple independent modules or integrated circuits.
摘要翻译：描述技术来提供从多模块或多集成电路系统中的分布式时间计数器收集分布式协调时间戳的设备和网络。模块之间的互连可以是单线或双线互连。通信地耦合到互连的模块可以使用冲突避免协议来触发模块之间的时间戳的广播，以及允许所有模块发送其时间戳。来自多个时钟的时钟可以由所有模块传输，然后进行采集和比较，以产生每个模块的时钟信号的校正因子，从而在多个独立模块或集成电路中潜在地实现分布式时钟同步。

5. 发明申请

WO2008013587A3 SUPPORTING MULTIPLE KEY LADDERS USING A COMMON PRIVATE KEY SET 审中-公开
公开(公告)号：WO2008013587A3
公开(公告)日：2008-01-31
申请号：PCT/US2007/008010
申请日：2007-03-30
申请人： INTEL CORPORATION , MUNGUIA, Peter , BROWN, Steve, J. , BHATT, Dhiraj , LOUKIANOV, Dmitrii
发明人： MUNGUIA, Peter , BROWN, Steve, J. , BHATT, Dhiraj , LOUKIANOV, Dmitrii
IPC分类号： H04L9/08
摘要： An apparatus may include circuitry to permanently and inaccessibly store a first private key that is a shared secret between a manufacturer of the circuitry and a first vendor of first encrypted media information. It may also include a key ladder to provide plural layers of encryption to the first private key to generate a first result for decrypting the first encrypted media information. A cryptographic module may encrypt the first private key to generate a second result for a security purpose other than decrypting media information. The module also may include a key ladder, and the apparatus may include other key ladders using the private key.

6. 发明申请

WO2005067185A1 PROGRAM CLOCK REFERENCE SYNCHRONIZATION IN MULTIMEDIA NETWORKS 审中-公开
标题翻译：多媒体网络中的程序时钟参考同步
公开(公告)号：WO2005067185A1
公开(公告)日：2005-07-21
申请号：PCT/US2004/041107
申请日：2004-12-08
申请人： INTEL CORPORATION , LOUKIANOV, Dmitrii , STEPHENS, Adrian
发明人： LOUKIANOV, Dmitrii , STEPHENS, Adrian
IPC分类号： H04J3/06
CPC分类号： H04N21/4302 , H04N21/242
摘要： Method of program clock synchronization when distributing media information among devices through;a communication link. The processor (117) in the transmitter (110) calculates the difference between sequential samples of program clock (CFsend) and also the difference between sequential samples of network system clock (CFw1) computing a frequency proportionality coefficient K1= Difl_CFsend/Diff_CFw1 which is sent to the receiver. The processor, (137) in the receiver (130) calculates the same values like in the transmitter (110) but using the locally maintained program clock (CFreceive) and system clock (CFw2) as well a K2= Diff_CFreceive/Diff_CFw2. Processor (137) compare K1 and K2 and generate a difference signal DeltaK= K1 - K2 used to adjust the program clock of the receiver.
摘要翻译：通过设备之间传送媒体信息时的节目时钟同步方法;通信链路。发射机（110）中的处理器（117）计算节目时钟（CFsend）的顺序采样之间的差异，以及计算发送的频率比例系数K1 = Difl_CFsend / Diff_CFw1的网络系统时钟（CFw1）的顺序采样之间的差异到接收器。接收器（130）中的处理器（137）计算与发送器（110）中相同的值，但是使用本地维护的程序时钟（CFreceive）和系统时钟（CFw2）以及K2 = Diff_CFreceive / Diff_CFw2。处理器（137）比较K1和K2并产生用于调整接收器的程序时钟的差分信号DeltaK = K1-K2。

7. 发明申请

WO2014209631A1 SECURE ACCESS ENFORCEMENT PROXY 审中-公开
标题翻译：安全访问执行代码
公开(公告)号：WO2014209631A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/042236
申请日：2014-06-13
申请人： INTEL CORPORATION , PEARSON, Adrian , THORNBURG, Christopher , NG, Raymond , RUESGA, Christopher , BROWN, Steve , LOUKIANOV, Dmitrii , KFIR, Ziv , HERMESH, Barak
发明人： PEARSON, Adrian , THORNBURG, Christopher , NG, Raymond , RUESGA, Christopher , BROWN, Steve , LOUKIANOV, Dmitrii , KFIR, Ziv , HERMESH, Barak
IPC分类号： G06F21/82
CPC分类号： G06F21/60 , G06F21/57 , G06F21/74 , G06F21/76 , G06F21/85 , G06F2221/2111
摘要： Efficient architecture for a secure access enforcement proxy is described. The proxy interfaces with multiple subsystems and multiple shared resources. The proxy identifies an original transaction command being sent from one of the subsystems to one of the shared resources, identifies a policy corresponding to the subsystem, performs an action pertaining to the original transaction command based on the policy, and sends a response to the subsystem based on the action.
摘要翻译：描述了用于安全访问强制代理的高效架构。代理接口具有多个子系统和多个共享资源。代理识别从一个子系统发送到共享资源之一的原始事务命令，识别与子系统相对应的策略，基于策略执行与原始事务命令有关的动作，并且向子系统发送响应基于行动。

8. 发明申请

WO2008018925A2 CONTROL WORD KEY STORE FOR MULTIPLE DATA STREAMS 审中-公开
标题翻译：控制字多个数据流的密钥存储区
公开(公告)号：WO2008018925A2
公开(公告)日：2008-02-14
申请号：PCT/US2007/008013
申请日：2007-03-30
申请人： INTEL CORPORATION , MINGUIA, Peter , BROWN, Steve, J. , BHATT, Dhiraj , LOUKIANOV, Dmitrii
发明人： MINGUIA, Peter , BROWN, Steve, J. , BHATT, Dhiraj , LOUKIANOV, Dmitrii
CPC分类号： H04N7/1675 , G06F21/6209 , G06F21/72 , H04L9/088 , H04L9/14 , H04N7/165 , H04N21/43607 , H04N21/4623
摘要： An apparatus may include circuitry, a cryptographic module, and a key store. The circuitry may hold a private key associated with first media information. The cryptographic module may operate on the private key to generate a number of first control keys for decrypting the first media information. The key store may hold the number of first control keys from the cryptographic module. In some implementations, the key store may include sufficient storage to store more than one control key from each of a number of different crypto modules. In some implementations, the key store may receive multiple control keys simultaneously or nearly so. In some implementations, the key store may output multiple control keys simultaneously, or nearly so, for decrypting multiple streams of media information at the same time.
摘要翻译：装置可以包括电路，密码模块和密钥存储器。该电路可以保存与第一媒体信息相关联的私钥。密码模块可以对私钥进行操作以生成用于解密第一媒体信息的多个第一控制密钥。密钥存储可以保存来自密码模块的第一控制密钥的数量。在一些实现中，密钥存储器可以包括足够的存储器来存储来自多个不同密码模块中的每一个的多于一个控制密钥。在一些实现中，密钥存储可以同时或几乎接收多个控制密钥。在一些实现中，密钥存储可以同时或几乎同时输出多个控制密钥，以同时解密多个媒体信息流。

9. 发明申请

WO2003007547A2 SYSTEM AND METHOD FOR PROCESSING BANDWIDTH ALLOCATION MESSAGES 审中-公开
标题翻译：用于处理带宽分配消息的系统和方法
公开(公告)号：WO2003007547A2
公开(公告)日：2003-01-23
申请号：PCT/US2002/021021
申请日：2002-07-03
申请人： INTEL CORPORATION
发明人： LOUKIANOV, Dmitrii , CHAPPELL, Christopher , HOFFMAN, Jeffrey
IPC分类号： H04L12/00
CPC分类号： H04L41/0896
摘要： Disclosed are a system and method of processing upstream bandwidth allocation messages in a downstream management message received at a client termination device. Bandwidth allocation elements based upon selected ones of the bandwidth allocation messages are stored in a data buffer. The stored bandwidth allocation elements may be accessed from the buffer in response to a validation of a cyclic redundancy code in the downstream management message.
摘要翻译：公开了一种在客户终端设备接收的下游管理消息中处理上行带宽分配消息的系统和方法。基于选定的带宽分配消息的带宽分配元素存储在数据缓冲器中。响应于下游管理消息中的循环冗余码的验证，可以从缓冲器访问所存储的带宽分配元素。

10. 发明申请

WO2003007547A3 SYSTEM AND METHOD FOR PROCESSING BANDWIDTH ALLOCATION MESSAGES 审中-公开
公开(公告)号：WO2003007547A3
公开(公告)日：2003-01-23
申请号：PCT/US2002/021021
申请日：2002-07-03
申请人： INTEL CORPORATION
发明人： LOUKIANOV, Dmitrii , CHAPPELL, Christopher , HOFFMAN, Jeffrey
IPC分类号： H04L12/28
摘要： Disclosed are a system and method of processing upstream bandwidth allocation messages in a downstream management message received at a client termination device. Bandwidth allocation elements based upon selected ones of the bandwidth allocation messages are stored in a data buffer. The stored bandwidth allocation elements may be accessed from the buffer in response to a validation of a cyclic redundancy code in the downstream management message.

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