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1. 发明申请

WO2012005938A3 FAULT TOLERANCE OF MULTI-PROCESSOR SYSTEM WITH DISTRIBUTED CACHE 审中-公开
公开(公告)号：WO2012005938A3
公开(公告)日：2012-01-12
申请号：PCT/US2011/041228
申请日：2011-06-21
申请人： INTEL CORPORATION , RANGARAJAN, Thanunathan , GANESAN, Baskaran , BHATTACHARAYYA, Binata
发明人： RANGARAJAN, Thanunathan , GANESAN, Baskaran , BHATTACHARAYYA, Binata
IPC分类号： G06F11/07 , G06F12/08 , G06F9/46
摘要： A semiconductor chip is described having different instances of cache agent logic circuitry for respective cache slices of a distributed cache. The semiconductor chip further includes hash engine logic circuitry comprising: hash logic circuitry to determine, based on an address, that a particular one of the cache slices is to receive a request having the address, and, a first input to receive notice of a failure event for the particular cache slice. The semiconductor chip also includes first circuitry to assign the address to another cache slice of the cache slices in response to the notice.

2. 发明申请

WO2011025626A3 PROVIDING STATE STORAGE IN A PROCESSOR FOR SYSTEM MANAGEMENT MODE 审中-公开
公开(公告)号：WO2011025626A3
公开(公告)日：2011-03-03
申请号：PCT/US2010/044089
申请日：2010-08-02
申请人： INTEL CORPORATION , NATU, Mahesh, S. , GANESAN, Baskaran , RANGARAJAN, Thanunathan , KUMAR, Mohan, J. , DOSHI, Gautam, B. , PARTHASARATHY, Rajesh, S. , DATTA, Shammanna, M. , BINNS, Frank , MURTHY, Rajesh Nagaraja , SWANSON, Robert, C.
发明人： NATU, Mahesh, S. , GANESAN, Baskaran , RANGARAJAN, Thanunathan , KUMAR, Mohan, J. , DOSHI, Gautam, B. , PARTHASARATHY, Rajesh, S. , DATTA, Shammanna, M. , BINNS, Frank , MURTHY, Rajesh Nagaraja , SWANSON, Robert, C.
IPC分类号： G06F13/10
摘要： In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

3. 发明申请

WO2016192056A1 SELF-LOCATING COMPUTING DEVICES, SYSTEMS, AND METHODS 审中-公开
标题翻译：自定位计算设备，系统和方法
公开(公告)号：WO2016192056A1
公开(公告)日：2016-12-08
申请号：PCT/CN2015/080661
申请日：2015-06-03
申请人： INTEL CORPORATION , ZHOU, Shen , SHENG, Zhijie , RANGARAJAN, Thanunathan , HUANG, Junjie
发明人： ZHOU, Shen , SHENG, Zhijie , RANGARAJAN, Thanunathan , HUANG, Junjie
IPC分类号： H04W4/02
CPC分类号： H04W4/043 , G06F9/45533 , G06F21/44 , G06F21/57 , H04W4/50 , H04W4/80
摘要： Embodiments of self-locating computing devices, systems, and methods are described. In some embodiments, a computing device may include a Wireless Credential Exchange Module (WCEM) to detect one or more location tags and a management engine, coupled to the WCEM, to retrieve information of the one or more location tags from the WCEM, and to provide an asset management server with an identifier of the computing device and the information of the one or more location tags or location information of the computing device. Other embodiments may be described and/or claimed.
摘要翻译：描述了自定位计算设备，系统和方法的实施例。在一些实施例中，计算设备可以包括用于检测耦合到WCEM的一个或多个位置标签和管理引擎的无线凭证交换模块（WCEM），以从WCEM检索一个或多个位置标签的信息，以及向资产管理服务器提供计算设备的标识符和计算设备的一个或多个位置标签或位置信息的信息。可以描述和/或要求保护其他实施例。

4. 发明申请

WO2012161737A1 INCORPORATING MEMORY AND IO CYCLE INFORMATION INTO COMPUTE USAGE DETERMINATIONS 审中-公开
标题翻译：将内存和IO周期信息纳入计算机使用决定
公开(公告)号：WO2012161737A1
公开(公告)日：2012-11-29
申请号：PCT/US2011/067030
申请日：2011-12-22
申请人： INTEL CORPORATION , REGO, Charles, W. , RANGARAJAN, Thanunathan , AHUJA, Nishi , JOHN, Jaiber, J. , VINCENT, Jay, L. , GANGULI, Mrittika
发明人： REGO, Charles, W. , RANGARAJAN, Thanunathan , AHUJA, Nishi , JOHN, Jaiber, J. , VINCENT, Jay, L. , GANGULI, Mrittika
IPC分类号： G06F11/34 , G06F9/06
CPC分类号： G06F11/3495 , G06F9/505 , G06F11/3433 , G06F11/3442 , G06F2201/815 , G06F2201/875 , G06F2201/88 , G06F2209/508
摘要： A system and method provide for receiving data corresponding to a computing node and identifying a processor usage, a memory usage and an input/output (10) usage based at least in part on the data corresponding to the computing node. In addition, a compute usage value may be determined for the computing node based at least in part on the processor usage, the memory usage and the IP usage.
摘要翻译：系统和方法提供用于接收对应于计算节点的数据，并且至少部分地基于对应于所述计算节点的数据来识别处理器使用，存储器使用和输入/输出（10）使用。此外，可以至少部分地基于处理器使用，存储器使用和IP使用来为计算节点确定计算使用值。

5. 发明申请

WO2016186793A1 GATHERING SENSED DATA FROM DEVICES TO MANAGE HOST COMMAND TRANSMISSION AND COOLING OF THE DEVICES 审中-公开
标题翻译：从设备获取感知数据以管理设备的命令传输和冷却
公开(公告)号：WO2016186793A1
公开(公告)日：2016-11-24
申请号：PCT/US2016/028707
申请日：2016-04-21
申请人： INTEL CORPORATION
发明人： RANGARAJAN, Thanunathan , OOI, Eng Hun , RANGARAJAN, Madhusudhan , CONE, Robert W. , AHUJA, Nishi
IPC分类号： G06F1/20 , G06F3/06 , G06F9/30
CPC分类号： G06F3/061 , G06F1/206 , G06F3/0625 , G06F3/0634 , G06F3/0653 , G06F3/0659 , G06F3/067 , G06F3/0689
摘要： Provided are a computer readable storage media, method, and system for gathering sensed data from devices to manage host command transmission and cooling of the device. Host commands are retrieved from a host memory in a host to perform Input/Output operations with respect to a device. The retrieved host commands are transmitted to the device to perform the I/O operations of the host command. A monitor command is transmitted to obtain sensed data from the device while processing the host commands. A rate of transmitting the host commands is adjusted in response to determining that the sensed data received from the device in response to the monitor command satisfies a condition.
摘要翻译：提供了一种用于从设备收集感测数据以管理主机命令传输和冷却设备的计算机可读存储介质，方法和系统。从主机中的主机存储器检索主机命令，以对设备执行输入/输出操作。检索到的主机命令被发送到设备以执行主机命令的I / O操作。发送监视命令以在处理主机命令时从设备获得感测数据。响应于确定响应于监视命令从设备接收到的感测数据满足条件，调整发送主机命令的速率。

6. 发明申请

WO2015047285A1 PROTECTION SCHEME FOR REMOTELY-STORED DATA 审中-公开
标题翻译：远程存储数据保护方案
公开(公告)号：WO2015047285A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/062067
申请日：2013-09-27
申请人： INTEL CORPORATION
发明人： NELLITHEERTHA, Hariprasad , DEEPAK, S, , RANGARAJAN, Thanunathan , KESHAVAMURTHY, Anil S.
IPC分类号： G06F21/60 , G06F15/16
CPC分类号： G06F21/602 , G06F9/45558 , G06F15/16 , G06F21/53 , G06F21/60 , G06F21/6218 , G06F2009/45587
摘要： The present disclosure is directed to a protection scheme for remotely-stored data A system may comprise, for example, at least one device including at least one virtual machine (VM) and a trusted execution environment (TEE)The TEE may include an encryption service to encrypt or decrypt data received from the at least one VM. In one embodiment, the at least one VM may include an encryption agent to interact with interfaces in the encryption service. For example, the encryption agent may register with the encryption service, at which time an encryption key corresponding to the at least one VM may be generated. After verifying the registration of the encryption agent, the encryption service may utilize the encryption key corresponding to the at least one VM to encrypt or decrypt data received from the encryption agent. The encryption service may then return the encrypted or decrypted data to the encryption agent.
摘要翻译：本公开涉及用于远程存储的数据的保护方案。系统可以包括例如包括至少一个虚拟机（VM）和可信执行环境（TEE）的至少一个设备.TEE可以包括加密服务以加密或解密从所述至少一个VM接收的数据。在一个实施例中，所述至少一个VM可以包括与加密服务中的接口交互的加密代理。例如，加密代理可以向加密服务注册，此时可以生成与至少一个VM相对应的加密密钥。在验证加密代理的注册之后，加密服务可以利用与至少一个VM相对应的加密密钥来加密或解密从加密代理接收的数据。加密服务然后可以将加密或解密的数据返回给加密代理。

7. 发明申请

WO2017172099A1 METHOD, SYSTEM, AND APPARATUS FOR AN IMPROVED MEMORY ERROR PREDICTION SCHEME 审中-公开
标题翻译：用于改进的存储器误差预测方案的方法，系统和装置
公开(公告)号：WO2017172099A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/018173
申请日：2017-02-16
申请人： INTEL CORPORATION
发明人： RANGARAJAN, Thanunathan
IPC分类号： G06F11/00 , G06F11/07 , G06F11/10 , G06F11/30
CPC分类号： G06F11/076 , G06F11/073 , G06F11/0793 , G06F11/1048 , G06F11/1076 , G06F11/3037 , G06F11/3058 , G06F11/3409 , G06F2201/81 , G06F2201/87
摘要： Method, system, and apparatus for predicting imminent memory failures based on one or more adverse conditions being subjected to the memory. One embodiment of a method comprises: tracking one or more corrected memory errors (CEs) in a memory; tracking one or more generated tokens, wherein the tokens are being generated at an initial rate; detecting one or more adverse conditions being subjected to the memory and responsive to the detection, reduce the rate at which the tokens are being generated; decrementing the tracked CEs based on a reoccurring leak timer, wherein upon each expiration of the reoccurring leak timer, the tracked CEs is decremented by one so long as there is at least one tracked token; reducing the tracked tokens by one in response to the decrement of the tracked CEs; and triggering a CE overflow signal upon detecting a count of the tracked CEs exceeding an overflow limit.
摘要翻译：基于存储器受到一个或多个不利条件来预测即将发生的存储器故障的方法，系统和设备。方法的一个实施例包括：跟踪存储器中的一个或多个经校正的存储器错误（CE）跟踪一个或多个生成的令牌，其中所述令牌以初始速率生成; 检测正在经历所述存储器并响应于所述检测的一个或多个不利条件，降低所述令牌正被产生的速率; 基于重新发生的泄漏定时器来递减所跟踪的CE，其中在所述重新发生的泄漏定时器的每个终止时，只要存在至少一个追踪的令牌，则追踪的CE被递减1; 响应被跟踪的CE的递减，将被跟踪的令牌减1; 并在检测到跟踪的CE的计数超过溢出限制时触发CE溢出信号。

8. 发明申请

WO2016025090A1 CONTROLLING TEMPERATURE OF A SYSTEM MEMORY 审中-公开
标题翻译：控制系统存储器的温度
公开(公告)号：WO2016025090A1
公开(公告)日：2016-02-18
申请号：PCT/US2015/037879
申请日：2015-06-26
申请人： INTEL CORPORATION
发明人： RANGARAJAN, Thanunathan , RISBUD, Vinayak P. , YASMIN, Tabassum
IPC分类号： G06F1/20 , G06F12/00
CPC分类号： G06F1/206 , G06F11/3037 , G06F11/3058 , G11C5/04 , G11C7/04 , G11C29/20 , G11C29/46 , G11C29/52 , G11C29/76 , G11C2029/0407 , G11C2029/0409 , Y02D10/16
摘要： In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括执行指令的至少一个核和耦合到所述至少一个核的存储器控制器。反过来，存储器控制器包括备用逻辑，用于响应于第一存储器件的温度超过热阈值，将存储在耦合到处理器的第一存储器件上的数据的动态传输耦合到耦合到处理器的第二存储器件。描述和要求保护其他实施例。

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