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1. 发明申请

WO2014105158A1 SIGNALING SOFTWARE RECOVERABLE ERRORS 审中-公开
标题翻译：信号软件可恢复的错误
公开(公告)号：WO2014105158A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/047311
申请日：2013-06-24
申请人： INTEL CORPORATION , RAJ, Ashok , HOLM, John G. , NEIGER, Gilbert , SANKARAN, Rajesh M. , KUMAR, Mohan J.
发明人： RAJ, Ashok , HOLM, John G. , NEIGER, Gilbert , SANKARAN, Rajesh M. , KUMAR, Mohan J.
IPC分类号： G06F11/00
CPC分类号： G06F11/006 , G06F11/0715 , G06F11/0772 , G06F11/0793
摘要： Embodiments of an invention for signaling software recoverable errors are disclosed. In one embodiment, a processor includes a first unit, a programmable indicator, and a second unit. The first unit is to detect a poison error. The programmable indicator is to indicate whether the poison error is signaled as a machine check error or as one of a fault and a system management interrupt. The second unit is to signal the poison error as one of a fault and a system management error responsive to the programmable indicator.
摘要翻译：公开了用于信令软件可恢复错误的发明的实施例。在一个实施例中，处理器包括第一单元，可编程指示器和第二单元。第一个单位是检测毒物的错误。可编程指示灯是指示是否发出毒物误差作为机器检查错误或作为故障和系统管理中断之一发出信号。第二个单元将响应于可编程指示器的毒性错误信号作为故障之一和系统管理错误。

2. 发明申请

WO2012134641A2 TECHNIQUES AND MECHANISMS FOR LIVE MIGRATION OF PAGES PINNED FOR DMA 审中-公开
标题翻译：用于DMA的PIN移动的技术和机制
公开(公告)号：WO2012134641A2
公开(公告)日：2012-10-04
申请号：PCT/US2012/024476
申请日：2012-02-09
申请人： INTEL CORPORATION , RAJ, Ashok , SANKARAN, Rajesh M.
发明人： RAJ, Ashok , SANKARAN, Rajesh M.
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F12/1081 , G06F13/28 , G06F2212/654
摘要： Techniques for migrating data from a first range of physical memory locations to a second range of physical memory locations. The second range of physical memory locations is allocated for migration of data from the first range of physical memory locations Pending transactions for the first range of physical memory locations are flushed. One or more address translation entries are reprogrammed. Data is migrated from the first range of physical memory locations to the second range of physical memory locations. Subsequent memory transactions are processed to cause the transactions to be directed to the second range of physical memory locations.
摘要翻译：用于将数据从第一范围的物理存储器位置迁移到物理存储器位置的第二范围的技术。物理存储器位置的第二范围被分配用于从物理存储器位置的第一范围的数据的迁移。待处理的物理存储器位置的第一范围的事务被刷新。一个或多个地址转换条目被重新编程。数据从物理内存位置的第一个范围迁移到物理内存位置的第二个范围。处理随后的内存事务以使事务被引导到物理内存位置的第二范围。

3. 发明申请

WO2022198548A1 PASID GRANULARITY RESOURCE CONTROL FOR IOMMU 审中-公开
公开(公告)号：WO2022198548A1
公开(公告)日：2022-09-29
申请号：PCT/CN2021/082908
申请日：2021-03-25
申请人： INTEL CORPORATION , GUO, Kaijie , RAJ, Ashok , SMITH, Ned , LI, Weigang , WANG, Junyuan , ZENG, Xin , WILL, Brian , FAN, Zijuan , KOUNAVIS, Michael E. , XIE, Qianjun , WANG, Yuan , HUO, Yao
发明人： GUO, Kaijie , RAJ, Ashok , SMITH, Ned , LI, Weigang , WANG, Junyuan , ZENG, Xin , WILL, Brian , FAN, Zijuan , KOUNAVIS, Michael E. , XIE, Qianjun , WANG, Yuan , HUO, Yao
IPC分类号： G06F13/00
摘要： An embodiment of an integrated circuit may comprise memory to store respective resource control descriptors in correspondence with respective identifiers, and an input/output (IO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to determine resource control information for an IO transaction based on a resource control descriptor stored in the memory that corresponds to an identifier associated with the IO transaction, and control utilization of one or more resources of the IOMMU based on the determined resource control information. Other embodiments are disclosed and claimed.

4. 发明申请

WO2019134066A1 HARDWARE-BASED VIRTUALIZATION OF INPUT/OUTPUT (I/O) MEMORY MANAGEMENT UNIT 审中-公开
公开(公告)号：WO2019134066A1
公开(公告)日：2019-07-11
申请号：PCT/CN2018/070012
申请日：2018-01-02
申请人： INTEL CORPORATION , TIAN, Kun , SANKARAN, Rajesh , KUMAR, Sanjay , RAJ, Ashok
发明人： TIAN, Kun , SANKARAN, Rajesh , KUMAR, Sanjay , RAJ, Ashok
IPC分类号： G06F13/28
摘要： A processor includes a hardware input/output (I/O) memory management unit (IOMMU) and a core, which executes an instruction to intercept a payload from a virtual machine (VM). The payload contains a guest bus device function (BDF) identifier, a guest address space identifier (ASID), and a guest address range. The core accesses, within a virtual machine control structure stored in memory, pointers to a first set of translation tables and a second set of translation tables. The core traverses the first set of translation tables to translate the guest BDF identifier to a host BDF identifier and traverses the second set of translation tables to translate the guest ASID to a host ASID. The core stores the host BDF identifier and the host ASID in the payload and submits, to the hardware IOMMU, an administrative command containing the payload to perform invalidation of the guest address range.

5. 发明申请

WO2019183831A1 ADDRESS SPACE IDENTIFIER MANAGEMENT IN COMPLEX INPUT/OUTPUT VIRTUALIZATION ENVIRONMENTS 审中-公开
公开(公告)号：WO2019183831A1
公开(公告)日：2019-10-03
申请号：PCT/CN2018/080862
申请日：2018-03-28
申请人： INTEL CORPORATION , TIAN, Kun , ZHENG, Xiao , RAJ, Ashok , KUMAR, Sanjay , SANKARAN, Rajesh
发明人： TIAN, Kun , ZHENG, Xiao , RAJ, Ashok , KUMAR, Sanjay , SANKARAN, Rajesh
IPC分类号： G06F12/08
摘要： Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.

6. 发明申请

WO2017171974A1 HANDLING OF ERROR PRONE CACHE LINE SLOTS OF MEMORY SIDE CACHE OF MULTI-LEVEL SYSTEM MEMORY 审中-公开
标题翻译：处理多级系统存储器的存储器侧缓存的错误PRONE缓存行时隙
公开(公告)号：WO2017171974A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/013442
申请日：2017-01-13
申请人： INTEL CORPORATION
发明人： YIGZAW, Theodros , RAJ, Ashok , SWANSON, Robert , KUMAR, Mohan J.
IPC分类号： G06F11/07 , G06F12/0802
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0811 , G06F2212/1021 , G06F2212/1032 , G06F2212/214 , G06F2212/22 , G06F2212/7201
摘要： An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.
摘要翻译：描述了一种包括存储器控制器逻辑电路以与多级系统存储器的存储器侧高速缓存接口的设备。存储器控制器逻辑电路包括错误跟踪电路以跟踪存储器侧高速缓存中的高速缓存线槽的错误。存储器控制器逻辑电路还包括故障列表电路，以存储被认为是过分容易出错的故障缓存线槽的标识符。存储器控制器逻辑电路将声明存储器侧高速缓存中的未命中，以寻找映射到故障列表中标识的高速缓存行槽的请求。

7. 发明申请

WO2018058363A1 MEASURING PER-NODE BANDWIDTH WITHIN NON-UNIFORM MEMORY ACCESS (NUMA) SYSTEMS 审中-公开
标题翻译：在非均匀存储访问（NUMA）系统中测量每个节点的带宽
公开(公告)号：WO2018058363A1
公开(公告)日：2018-04-05
申请号：PCT/CN2016/100545
申请日：2016-09-28
申请人： INTEL CORPORATION
发明人： JIN, Yao , RAJ, Ashok , LUCK, Anthony E. G.
IPC分类号： G06F12/08
摘要： A computing system includes a plurality of nodes including a first node, the first node including at least one core, a memory controller, a node-track register (MSR), and a monitoring counter array including a plurality of counters. The memory controller is to access a plurality of bits of the node-track MSR to determine a subset of nodes to be tracked, wherein the subset of nodes includes the first node and a second node. The memory controller is further to allocate a first counter of the plurality of counters to track memory requests sent to a local system memory by the first node; and allocate a second counter of the plurality of counters to track a memory response associated with a memory request sent by the first node to the second node.
摘要翻译：计算系统包括多个节点，所述多个节点包括第一节点，所述第一节点包括至少一个核心，存储器控制器，节点轨道寄存器（MSR）以及监视计数器阵列，所述监视计数器阵列包括多个计数器。存储器控制器将访问节点轨道MSR的多个比特以确定要跟踪的节点的子集，其中节点的子集包括第一节点和第二节点。存储器控制器进一步分配多个计数器中的第一计数器以跟踪由第一节点发送到本地系统存储器的存储器请求; 并且分配多个计数器中的第二计数器以跟踪与由第一节点发送到第二节点的存储器请求相关联的存储器响应。

8. 发明申请

WO2023019537A1 APPARATUSES, METHODS, AND SYSTEMS FOR DEVICE TRANSLATION LOOKASIDE BUFFER PRE-TRANSLATION INSTRUCTION AND EXTENSIONS TO INPUT/OUTPUT MEMORY MANAGEMENT UNIT PROTOCOLS 审中-公开
公开(公告)号：WO2023019537A1
公开(公告)日：2023-02-23
申请号：PCT/CN2021/113666
申请日：2021-08-20
申请人： INTEL CORPORATION
发明人： GUO, Kaijie , XIE, Qianjun , LI, Weigang , WANG, Junyuan , RAJ, Ashok , FAN, Zijuan
IPC分类号： G06F3/06
摘要： Systems, methods, and apparatuses to support a device translation lookaside buffer pre-translation instruction are described. A hardware system includes an input/output device, an input/output memory controller to perform a direct memory access of a memory for the input/output device, and a processor core separate from the input/output device and comprising a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including one or more fields to identify a virtual address to physical address mapping for the input/output device in the memory, and an opcode to indicate an execution circuit is to store the virtual address to physical address mapping into a translation lookaside buffer within the input/output device, and the execution circuit to execute the decoded single instruction according to the opcode.

9. 发明申请

WO2022040911A1 METHODS AND APPARATUS TO PERFORM PSEUDO-S3 PROTOCOL TO UPDATE FIRMWARE AND/OR ACTIVATE NEW FIRMWARE WITH WARM RESET 审中-公开
公开(公告)号：WO2022040911A1
公开(公告)日：2022-03-03
申请号：PCT/CN2020/111063
申请日：2020-08-25
申请人： INTEL CORPORATION
发明人： KUMAR, Mohan , JAYAKUMAR, Sarathy , WANG, Peng, Brett , RAJ, Ashok , NACHIMUTHU, Murugasamy
IPC分类号： G06F8/656 , G06F9/4401
摘要： Methods, apparatus, systems, and articles of manufacture to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset are disclosed. An example apparatus includes an advanced configuration and power interface (ACPI) to: initiate a pseudo-sleep event in response to identifying a firmware update; and assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; a basic input/output system (BIOS) to: initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update; and transmit a wake vector to the OS to continue operation.

10. 发明申请

WO2019190685A1 SYSTEM, APPARATUS AND METHOD FOR PROVIDING HARDWARE FEEDBACK INFORMATION IN A PROCESSOR 审中-公开
公开(公告)号：WO2019190685A1
公开(公告)日：2019-10-03
申请号：PCT/US2019/019961
申请日：2019-02-28
申请人： INTEL CORPORATION
发明人： SHANBHOGUE, Vedvyas , ANANTHAKRISHNAN, Avinash N. , GORBATOV, Eugene , FENGER, Russell , RAJ, Ashok , SUBRAMANIAM, Kameswar
IPC分类号： G06F9/445 , G06F11/30 , G06F11/34
摘要： In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.

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