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1. 发明申请

WO2006057847A1 SCALABLE, HIGH-PERFORMANCE, GLOBAL INTERCONNECT SCHEME FOR MULTI-THREADED, MULTIPROCESSING SYSTEM-ON-A-CHIP NETWORK PROCESSOR UNIT 审中-公开
标题翻译：可扩展，高性能，多线程，多制式系统在线芯片网络处理器单元的全球互连方案
公开(公告)号：WO2006057847A1
公开(公告)日：2006-06-01
申请号：PCT/US2005/041182
申请日：2005-11-10
申请人： INTEL CORPORATION , LAKSHMANAMURTHY, Sridhar , ROSENBLUTH, Mark , ADILETTA, Matthew , MINN, Jeen-yuan , BOSE, Bijoy
发明人： LAKSHMANAMURTHY, Sridhar , ROSENBLUTH, Mark , ADILETTA, Matthew , MINN, Jeen-yuan , BOSE, Bijoy
IPC分类号： G06F15/78 , G06F15/80
CPC分类号： G06F15/7842 , G06F15/8007
摘要： A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.
摘要翻译：用于多线程，多处理片上系统处理器单元的可扩展的高性能互连方案。实现该技术的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。在一个实施例中，机箱互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线路，用于目标的拉动数据总线写入和用于目标读取的推送数据总线。采用用于每个命令总线，拉数据总线和推数据总线的多路复用器电路来选择性地将给定集群连接到给定目标，以使命令和数据能够在给定集群和给定目标之间传递。

2. 发明申请

WO2007041145A1 INSTRUCTION-ASSISTED CACHE MANAGEMENT FOR EFFICIENT USE OF CACHE AND MEMORY 审中-公开
标题翻译：指令性协调的高速缓存管理，以便有效地使用缓存和内存
公开(公告)号：WO2007041145A1
公开(公告)日：2007-04-12
申请号：PCT/US2006/037631
申请日：2006-09-26
申请人： INTEL CORPORATION , LAKSHMANAMURTHY, Sridhar , ROSENBLUTH, Mark
发明人： LAKSHMANAMURTHY, Sridhar , ROSENBLUTH, Mark
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F9/30047 , G06F12/0804 , G06F12/0888 , G06F12/126
摘要： Instruction-assisted cache management for efficient use of cache and memory. Hints (e.g., modifiers) are added to read and write memory access instructions to identify the memory access is for temporal data. In view of such hints, alternative cache policy and allocation policies are implemented that minimize cache and memory access. Under one policy, a write cache miss may result in a write of data to a partial cache line without a memory read/write cycle to fill the remainder of the line. Under another policy, a read cache miss may result in a read from memory without allocating or writing the read data to a cache line. A cache line soft-lock mechanism is also disclosed, wherein cache lines may be selectably soft locked to indicate preference for keeping those cache lines over non-locked lines.
摘要翻译：指令辅助缓存管理，用于缓存和内存的高效使用。添加提示（例如，修饰符）来读取和写入存储器访问指令以识别用于时间数据的存储器访问。鉴于这样的提示，实现了使缓存和存储器访问最小化的替代高速缓存策略和分配策略。在一个策略下，写入高速缓存未命中可能导致将数据写入部分高速缓存行而没有存储器读/写周期来填充该行的剩余部分。在另一策略下，读高速缓存未命中可能导致从存储器的读取，而无需将读取的数据分配或写入高速缓存行。还公开了一种高速缓存行软锁定机制，其中高速缓存行可以被可选地软锁定以指示将这些高速缓存行保持在非锁定行上的偏好。

3. 发明申请

WO2006039183A3 EXPANSION OF COMPUTE ENGINE CODE SPACE BY SHARING ADJACENT CONTROL STORES USING INTERLEAVED PROGRAM ADDRESSES 审中-公开
公开(公告)号：WO2006039183A3
公开(公告)日：2006-04-13
申请号：PCT/US2005/034010
申请日：2005-09-21
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ROSENBLUTH, Mark , ADILETTA, Matthew , WILKINSON, Hugh , NIELL, Jose , NARAYANAN, Rajagopal , JAIN, Sanjeev
发明人： WOLRICH, Gilbert , ROSENBLUTH, Mark , ADILETTA, Matthew , WILKINSON, Hugh , NIELL, Jose , NARAYANAN, Rajagopal , JAIN, Sanjeev
IPC分类号： G06F9/32
摘要： Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.

4. 发明申请

WO2006055477A1 HETEROGENEOUS PROCESSORS SHARING A COMMON CACHE 审中-公开
标题翻译：共享缓存的异构处理器
公开(公告)号：WO2006055477A1
公开(公告)日：2006-05-26
申请号：PCT/US2005/041166
申请日：2005-11-10
申请人： INTEL CORPORATION , HADY, Frank , CABOT, Mason , BECK, John , ROSENBLUTH, Mark
发明人： HADY, Frank , CABOT, Mason , BECK, John , ROSENBLUTH, Mark
IPC分类号： G06F15/78
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0893 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F15/781 , G06F15/7842 , G06F15/7846 , G06F2212/283 , G06F2212/302 , G06F2212/314 , G06F2212/621
摘要： A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
摘要翻译：提出了一种提供异构处理器内核和共享缓存的多核处理器。

5. 发明申请

WO2007015900A3 LOCK SEQUENCING 审中-公开
公开(公告)号：WO2007015900A3
公开(公告)日：2007-02-08
申请号：PCT/US2006/027984
申请日：2006-07-17
申请人： INTEL CORPORATION , ROSENBLUTH, Mark , WOLRICH, Gilbert , JAIN, Sandeev
发明人： ROSENBLUTH, Mark , WOLRICH, Gilbert , JAIN, Sandeev
IPC分类号： G06F9/52
摘要： In general, in one aspect, the disclosure describes a processor that includes multiple multi-threaded programmable units integrated on a single die. The die also includes circuitry communicatively coupled to the programmable units that reorders and grants lock requests received from the threads based on an order in which the threads requested insertion into a sequence of lock grants.

6. 发明申请

WO2005098684A1 CONTENT ADDRESSABLE MEMORY CONSTRUCTED FROM RANDOM ACCESS MEMORY 审中-公开
标题翻译：内存可访问记忆由随机存取存储器构成
公开(公告)号：WO2005098684A1
公开(公告)日：2005-10-20
申请号：PCT/US2005/009412
申请日：2005-03-18
申请人： INTEL CORPORATION , ROSENBLUTH, Mark
发明人： ROSENBLUTH, Mark
IPC分类号： G06F17/30
CPC分类号： G06F17/30982
摘要： The disclosure includes a description of a content addressable memory (CAM) that includes at least one tag input, at least one output, and at least one random access memory. The CAM includes circuitry to perform multiple read operations of the at least one random access memory with different ones of the read operations specifying an address being based on different subsets of tag bits. Based on the multiple read operations, the CAM generates at least one signal via the at least one output.
摘要翻译：本公开包括对包括至少一个标签输入，至少一个输出和至少一个随机存取存储器的内容可寻址存储器（CAM）的描述。 CAM包括用于执行至少一个随机存取存储器的多个读取操作的电路，其中不同的读取操作指定地址是基于不同的标签位子集。基于多个读取操作，CAM经由至少一个输出产生至少一个信号。

7. 发明申请

WO2006113570A2 RING MANAGEMENT 审中-公开
标题翻译：环形管理
公开(公告)号：WO2006113570A2
公开(公告)日：2006-10-26
申请号：PCT/US2006/014318
申请日：2006-04-13
申请人： INTEL CORPORATION , ROSENBLUTH, Mark , NARAD, Charles
发明人： ROSENBLUTH, Mark , NARAD, Charles
IPC分类号： G06F5/10 , G06F12/00
CPC分类号： G06F5/10 , G06F12/0831
摘要： The disclosure describes techniques used by one or more producers and consumers of one or more rings.
摘要翻译：本公开描述了一个或多个环的一个或多个生产者和消费者使用的技术。

8. 发明申请

WO2006069355A2 METHOD AND APPARATUS TO PROVIDE EFFICIENT COMMUNICATION BETWEEN PROCESSING ELEMENTS IN A PROCESSOR UNIT 审中-公开
标题翻译：在处理器单元中处理元素之间提供有效通信的方法和装置
公开(公告)号：WO2006069355A2
公开(公告)日：2006-06-29
申请号：PCT/US2005/046937
申请日：2005-12-20
申请人： INTEL CORPORATION , ROSENBLUTH, Mark , JAIN, Sanjeev , WOLRICH, Gilbert
发明人： ROSENBLUTH, Mark , JAIN, Sanjeev , WOLRICH, Gilbert
CPC分类号： G06F13/4252
摘要： A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is transferred over a first bus from processing element to processing element.
摘要翻译：上下文转发总线在具有多个处理单元的处理器单元中有效地传送处理单元之间的控制和数据。控制和数据信息通过第一总线从处理元件传送到处理元件。

9. 发明申请

WO2006069126A2 METHOD AND APPARATUS TO SUPPORT MULTIPLE MEMORY BANKS WITH A MEMORY BLOCK 审中-公开
标题翻译：用存储器块支持多个存储器银行的方法和设备
公开(公告)号：WO2006069126A2
公开(公告)日：2006-06-29
申请号：PCT/US2005/046297
申请日：2005-12-20
申请人： INTEL CORPORATION , JAIN, Sanjeev , WOLRICH, Gilbert , ROSENBLUTH, Mark , BERNSTEIN, Debra
发明人： JAIN, Sanjeev , WOLRICH, Gilbert , ROSENBLUTH, Mark , BERNSTEIN, Debra
IPC分类号： G06F13/16
CPC分类号： G06F13/1673
摘要： A memory controller system includes a memory command storage module to store commands for a plurality of memory banks. The system includes a plurality of control mechanisms, each of which includes first and second pointers, to provide, in combination with a next field in each module location, a link list of commands for a given one of the plurality of memory banks.
摘要翻译：存储器控制器系统包括用于存储用于多个存储体的命令的存储器命令存储模块。该系统包括多个控制机构，每个控制机构包括第一和第二指针，以与每个模块位置中的下一个字段结合提供用于多个存储体中给定的一个存储体的命令的链接列表。 p>

10. 发明申请

WO2006063298A1 TECHNIQUES TO MANAGE FLOW CONTROL 审中-公开
标题翻译：管理流量控制技术
公开(公告)号：WO2006063298A1
公开(公告)日：2006-06-15
申请号：PCT/US2005/044750
申请日：2005-12-09
申请人： INTEL CORPORATION , JAIN, Sanjeev , ROSENBLUTH, Mark , WOLRICH, Gilbert , WILKINSON, Hugh
发明人： JAIN, Sanjeev , ROSENBLUTH, Mark , WOLRICH, Gilbert , WILKINSON, Hugh
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L49/15 , H04L49/254 , H04L49/30 , H04L2012/5678
摘要： A network device comprises an ingress processor (400) and an egress processor (450) connected via a flow control bus (485). Flow control messages received by a traffic manager module (489) comprised by the ingress processor are sent to a transmit path (498) and a control path (497).
摘要翻译：网络设备包括通过流量控制总线（485）连接的入口处理器（400）和出口处理器（450）。由入口处理器组成的流量管理器模块（489）接收的流量控制消息被发送到发送路径（498）和控制路径（497）。

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