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1. 发明申请

WO2006063298A1 TECHNIQUES TO MANAGE FLOW CONTROL 审中-公开
标题翻译：管理流量控制技术
公开(公告)号：WO2006063298A1
公开(公告)日：2006-06-15
申请号：PCT/US2005/044750
申请日：2005-12-09
申请人： INTEL CORPORATION , JAIN, Sanjeev , ROSENBLUTH, Mark , WOLRICH, Gilbert , WILKINSON, Hugh
发明人： JAIN, Sanjeev , ROSENBLUTH, Mark , WOLRICH, Gilbert , WILKINSON, Hugh
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L49/15 , H04L49/254 , H04L49/30 , H04L2012/5678
摘要： A network device comprises an ingress processor (400) and an egress processor (450) connected via a flow control bus (485). Flow control messages received by a traffic manager module (489) comprised by the ingress processor are sent to a transmit path (498) and a control path (497).
摘要翻译：网络设备包括通过流量控制总线（485）连接的入口处理器（400）和出口处理器（450）。由入口处理器组成的流量管理器模块（489）接收的流量控制消息被发送到发送路径（498）和控制路径（497）。

2. 发明申请

WO2006039183A3 EXPANSION OF COMPUTE ENGINE CODE SPACE BY SHARING ADJACENT CONTROL STORES USING INTERLEAVED PROGRAM ADDRESSES 审中-公开
公开(公告)号：WO2006039183A3
公开(公告)日：2006-04-13
申请号：PCT/US2005/034010
申请日：2005-09-21
申请人： INTEL CORPORATION , WOLRICH, Gilbert , ROSENBLUTH, Mark , ADILETTA, Matthew , WILKINSON, Hugh , NIELL, Jose , NARAYANAN, Rajagopal , JAIN, Sanjeev
发明人： WOLRICH, Gilbert , ROSENBLUTH, Mark , ADILETTA, Matthew , WILKINSON, Hugh , NIELL, Jose , NARAYANAN, Rajagopal , JAIN, Sanjeev
IPC分类号： G06F9/32
摘要： Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.

3. 发明申请

WO2006065689A1 METHOD AND APPARATUS FOR IMPLEMENTING A BI-ENDIAN CAPABLE COMPILER 审中-公开
标题翻译：用于实施BI-ENDIAN可编译器的方法和装置
公开(公告)号：WO2006065689A1
公开(公告)日：2006-06-22
申请号：PCT/US2005/044772
申请日：2005-12-09
申请人： INTEL CORPORATION , WILKINSON, Hugh , ADILETTA, Matthew , KUSHLIS, Robert
发明人： WILKINSON, Hugh , ADILETTA, Matthew , KUSHLIS, Robert
IPC分类号： G06F9/45
CPC分类号： G06F8/436 , G06F8/447 , G06F8/52
摘要： A method of compiling code includes assigning an endian type to data. An endian flip operation is performed based on the endian type of the data and a target system. Other embodiments are described and claimed.
摘要翻译：一种编译代码的方法包括将端序类型分配给数据。根据数据的末端类型和目标系统执行端序翻转操作。描述和要求保护其他实施例。

4. 发明申请

WO2017172217A1 TECHNOLOGIES FOR A DISTRIBUTED HARDWARE QUEUE MANAGER 审中-公开
标题翻译：分布式硬件队列管理器的技术
公开(公告)号：WO2017172217A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/020230
申请日：2017-03-01
申请人： INTEL CORPORATION
发明人： WANG, Ren , WANG, Yipeng , TSAI, Jr-Shian , HERDRICH, Andrew J. , TAI, Tsung-Yuan C. , MCDONNELL, Niall , VAN DOREN, Stephen R. , SONNIER, David , BERNSTEIN, Debra , WILKINSON, Hugh , VANGATI, Narender , MILLER, Stephen , EADS, Gage , CUNNINGHAM, Andrew , KENNY, Jonathan , RICHARDSON, Bruce , BURROUGHS, William , HASTING, Joseph , YAN, An , CLEE, James , MA, Te , PIROG, Jerry , WHITESELL, Jamison
IPC分类号： G06F9/54 , G06F9/48
CPC分类号： G06F13/36 , G06F12/1027 , G06F13/24 , G06F13/4004 , G06F2212/1021 , G06F2212/50 , G06F2212/68
摘要： Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.
摘要翻译：分布式硬件队列管理器的技术包括具有处理器的计算设备。处理器包含两个或更多硬件队列管理器以及两个或更多处理器内核。每个处理器核心都可以从硬件队列管理器中入队或出队。每个硬件队列管理器都可以配置为包含多个队列数据结构。在一些实施例中，处理器内核使用虚拟队列地址寻址队列，所述虚拟队列地址被转换成用于访问相应硬件队列管理器的物理队列地址。虚拟队列可以从一个硬件队列管理器中的一个物理队列移动到另一个物理队列管理器中的不同物理队列，而不会更改虚拟队列的虚拟地址。

5. 发明申请

WO2003063018A2 FUNCTIONAL PIPELINES 审中-公开
标题翻译：功能管道
公开(公告)号：WO2003063018A2
公开(公告)日：2003-07-31
申请号：PCT/US2003/001578
申请日：2003-01-16
申请人： INTEL CORPORATION (A DELAWARE CORPORATION)
发明人： ADILETTA, Matthew , BERNSTEIN, Debra , WILDE, Myles , WOLRICH, Gilbert , ROSENBLUTH, Mark , WILKINSON, Hugh
IPC分类号： G06F15/76
CPC分类号： G06F15/8053
摘要： A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.
摘要翻译：一种用于在功能管线中采用多个硬件上下文和编程引擎的系统和方法，该功能管线被划分以便于高性能数据处理。该系统和方法包括并行处理器，其分配用于处理数据的系统功能，所述系统功能包括支持多个上下文的编程引擎，所述编程引擎被布置为通过在所述编程引擎之间传递功能数据的功能流水线控制单元提供功能

6. 发明申请

WO2018004931A1 TECHNIQUES FOR VIRTUAL ETHERNET SWITCHING OF A MULTI-NODE FABRIC 审中-公开
标题翻译：一种多节点织物的虚拟以太网交换技术
公开(公告)号：WO2018004931A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/035048
申请日：2017-05-30
申请人： INTEL CORPORATION
发明人： WILKINSON, Hugh , WRIGHT, James
IPC分类号： H04L12/931 , H04L12/66
CPC分类号： H04L49/351 , H04L12/4633 , H04L45/74 , H04L49/10 , H04L49/254 , H04L49/70 , H04L61/6022
摘要： Examples include techniques for virtual Ethernet switching of a multi-node fabric. In some examples, first Ethernet links coupled with a group of Ethernet gateways are link aggregated. The group of Ethernet gateways couple with respective individual physical switch ports of a fabric switch of a multi-node fabric to form a default logical gateway to provide an uplink between a virtual Ethernet switch and an Ethernet network external to the multi-node fabric. Also, one or more individual Ethernet gateways coupled with respective individual physical switch ports of the fabric switch may be arranged to provide one or more respective downlinks between the virtual Ethernet switch and one or more Ethernet nodes external to the multi-node fabric via respective second Ethernet links coupled with the one or more individual Ethernet gateways.
摘要翻译：示例包括用于多节点结构的虚拟以太网交换的技术。在一些示例中，与一组以太网网关耦合的第一以太网链路是链路聚合的。这组以太网网关与多节点结构的结构交换机的各个单独的物理交换机端口耦合以形成默认的逻辑网关，以提供虚拟以太网交换机与多节点结构外部的以太网之间的上行链路。而且，可以布置与织物交换机的各个单独物理交换机端口耦合的一个或多个单独的以太网网关，以在虚拟以太网交换机和多节点结构外部的一个或多个以太网节点之间经由相应的第二以太网链路与一个或多个单独的以太网网关连接。

7. 发明申请

WO2015153088A1 CABLELESS CONNECTION APPARATUS AND METHOD FOR COMMUNICATION BETWEEN CHASSIS 审中-公开
标题翻译：无线连接装置和组合之间的通信方法
公开(公告)号：WO2015153088A1
公开(公告)日：2015-10-08
申请号：PCT/US2015/019952
申请日：2015-03-11
申请人： INTEL CORPORATION
发明人： ADILETTA, Matthew J. , GORIUS, Aaron , WILDE, Myles , WILKINSON, Hugh , KUMAR, Amit Y.
IPC分类号： H05K7/14 , H05K7/18
CPC分类号： H04L49/10 , H04B1/40 , H04L49/35 , H04L67/10 , H05K7/1492
摘要： Apparatus and methods for cableless connection of components within chassis and between separate chassis. Pairs of Extremely High Frequency (EHF) transceiver chips supporting very short length millimeter-wave wireless communication links are configured to pass radio frequency signals through holes in one or more metal layers in separate chassis and/or frames, enabling components in the separate chassis to communicate without requiring cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. The EHF-based wireless links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.
摘要翻译：用于无线连接机箱内部和分离机箱之间的部件的装置和方法。支持非常短长度的毫米波无线通信链路的极高频（EHF）收发器芯片配置成通过单独的机箱和/或框架中的一个或多个金属层中的孔传递射频信号，使单独机架中的组件能够通信而不需要机箱之间的电缆。公开了各种配置，包括服务器机箱，存储机箱和阵列以及网络/交换机机箱的多种配置。基于EHF的无线链路支持高达每秒6吉比特的链路带宽，并且可以聚合以便于多车道链路。

8. 发明申请

WO2022139923A1 MEMORY ACCESSES USING A MEMORY HUB 审中-公开
公开(公告)号：WO2022139923A1
公开(公告)日：2022-06-30
申请号：PCT/US2021/051801
申请日：2021-09-23
申请人： INTEL CORPORATION
发明人： GALBI, Duane E. , ADILETTA, Matthew J. , WILKINSON, Hugh , CONNOR, Patrick
IPC分类号： G06F13/16 , G06F13/42 , G06F13/40
摘要： Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub.

9. 发明申请

WO2018063776A1 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO DETERMINE PAGE GROUP IDENTIFIERS, AND OPTIONALLY PAGE GROUP METADATA, ASSOCIATED WITH LOGICAL MEMORY ADDRESSES 审中-公开
标题翻译：用于确定页面组标识符的处理器，方法，系统和指令以及与逻辑存储器地址相关的可选页面组元数据
公开(公告)号：WO2018063776A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/050652
申请日：2017-09-08
申请人： INTEL CORPORATION
发明人： WILKINSON, Hugh , WHEELER, William, R. , AUNDHE, Shirish , VISWANATHAN, Sandhya , KOUFATY, David, A.
IPC分类号： G06F12/02 , G06F9/30 , G06F12/1027
CPC分类号： G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/30145 , G06F12/145 , G06F2212/1052 , G06F2212/68
摘要： A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate source memory address information, and the instruction to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result is to include one of: (1) a page group identifier that is to correspond to a logical memory address that is to be based, at least in part, on the source memory address information; and (2) a set of page group metadata that is to correspond to the page group identifier. Other processors, methods, systems, and instructions are disclosed.
摘要翻译：一个方面的处理器包括解码单元以解码指令。该指令用于指示源存储器地址信息以及指示目标体系结构可见存储位置的指令。处理器还包括与解码单元耦合的执行单元。执行单元响应于该指令将结果存储在目的地架构可见的存储位置中。结果是包括以下之一：（1）至少部分地基于源存储器地址信息来对应于逻辑存储器地址的页面组标识符; 和（2）与页面组标识符对应的一组页面组元数据。披露了其他处理器，方法，系统和指令。

10. 发明申请

WO2018004969A1 BIT CHECK PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO CHECK A BIT WITH AN INDICATED CHECK BIT VALUE 审中-公开
标题翻译： BIT检查处理器，方法，系统和说明以检查具有指示检查位值的位
公开(公告)号：WO2018004969A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/035395
申请日：2017-06-01
申请人： INTEL CORPORATION
发明人： WILKINSON, Hugh , WHEELER, William R. , BERNSTEIN, Debra
IPC分类号： G06F12/02 , G06F9/30
CPC分类号： G06F12/0253 , G06F9/30018 , G06F9/30021 , G06F2212/702 , G11C7/1072
摘要： A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.
摘要翻译：一方面的处理器包括用于存储条件码比特的寄存器以及用于解码比特检查指令的解码单元。位检查指令指示将包括第一位的第一源操作数，并且指示第一位的检查位值。处理器还包括与解码单元耦合的执行单元。响应于比特检查指令，执行单元将第一比特与校验比特值进行比较，并更新条件码比特以指示第一比特是否等于校验比特值。披露了其他处理器，方法，系统和指令。

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