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1. 发明申请

WO2019132904A1 SOURCE ELECTRODE AND DRAIN ELECTRODE PROTECTION FOR NANOWIRE TRANSISTORS 审中-公开
公开(公告)号：WO2019132904A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/068624
申请日：2017-12-28
申请人： INTEL CORPORATION , JAMBUNATHAN, Karthik , GUHA, Biswajeet , MURTHY, Anand S. , GHANI, Tahir
发明人： JAMBUNATHAN, Karthik , GUHA, Biswajeet , MURTHY, Anand S. , GHANI, Tahir
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/41 , H01L21/768
摘要： Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.

2. 发明申请

WO2017171759A1 GEOMETRY TUNING OF FIN BASED TRANSISTOR 审中-公开
标题翻译：基于FIN晶体管的几何调谐
公开(公告)号：WO2017171759A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025070
申请日：2016-03-30
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , MURTHY, Anand S. , JAMBUNATHAN, Karthik , MOHAPATRA, Chandra S. , KAM, Hei , MISTKAWI, Nabil G. , KANG, Jun Sung , GUHA, Biswajeet
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7851 , B82Y10/00 , H01L21/3081 , H01L21/823807 , H01L21/823821 , H01L21/8258 , H01L27/0924 , H01L29/0669 , H01L29/0673 , H01L29/0847 , H01L29/1037 , H01L29/4232 , H01L29/66439 , H01L29/66545 , H01L29/6681 , H01L29/66818 , H01L29/775 , H01L29/78
摘要： A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.
摘要翻译：沟槽形成在绝缘层中以暴露衬底上的自然鳍。替换翅片放置在沟槽中的原生翅片上。替换翅片横向修剪。

3. 发明申请

WO2019035837A1 INTEGRATED NANOWIRE & NANORIBBON PATTERNING IN TRANSISTOR MANUFACTURE 审中-公开
公开(公告)号：WO2019035837A1
公开(公告)日：2019-02-21
申请号：PCT/US2017/047409
申请日：2017-08-17
申请人： INTEL CORPORATION
发明人： GULER, Leonard P. , GUHA, Biswajeet , ARMSTRONG, Mark , GHANI, Tahir , HSU, William
IPC分类号： H01L27/088 , H01L27/02 , H01L29/06
摘要： Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

4. 发明申请

WO2018004680A1 SELF-ALIGNED GATE EDGE TRIGATE AND FINFET DEVICES 审中-公开
标题翻译：自对准栅极触发器和FINFET器件
公开(公告)号：WO2018004680A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040804
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： LIAO, Szuya S. , GUHA, Biswajeet , GHANI, Tahir , KENYON, Christopher N. , GULER, Leonard P.
IPC分类号： H01L29/78
CPC分类号： H01L27/0924 , H01L21/76895 , H01L21/823821 , H01L21/823878 , H01L23/535 , H01L29/66545 , H01L29/66795 , H01L29/7851
摘要： Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.
摘要翻译：描述了自对准的栅极边缘触发和finFET器件以及制造自对准的栅极边缘触发器和finFET器件的方法。在示例中，半导体结构包括设置在衬底上方并且穿过沟槽隔离区域的最上表面突出的多个半导体鳍。栅极结构设置在多个半导体鳍上。栅极结构限定多个半导体鳍片中的每一个中的沟道区域。源极和漏极区位于栅极结构的相对侧的多个半导体鳍中的每一个的沟道区的相对端上。该半导体结构还包括多个栅极边缘隔离结构。多个栅极边缘隔离结构中的各个栅极边缘隔离结构与多个半导体鳍片中的各个半导体鳍片交替。

5. 发明申请

WO2019066788A1 EPITAXIAL OXIDE PLUG FOR STRAINED TRANSISTORS 审中-公开
公开(公告)号：WO2019066788A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/053582
申请日：2017-09-27
申请人： INTEL CORPORATION
发明人： JAMBUNATHAN, Karthik , GUHA, Biswajeet , BOWONDER, Anupama , MURTHY, Anand S. , GHANI, Tahir
IPC分类号： H01L29/78 , H01L29/66 , H01L21/768
摘要： Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

6. 发明申请

WO2019040041A1 SELF-ALIGNED NANOWIRE 审中-公开
公开(公告)号：WO2019040041A1
公开(公告)日：2019-02-28
申请号：PCT/US2017/047758
申请日：2017-08-21
申请人： INTEL CORPORATION
发明人： ARMSTRONG, Mark , GUHA, Biswajeet , KANG, Jun, Sung , BEATTIE, Bruce, E. , GHANI, Tahir
IPC分类号： H01L29/06 , H01L21/8238 , H01L21/02 , H01L27/092
摘要： A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

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