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1. 发明申请

WO2007134106A2 TECHNIQUES TO GENERATE NETWORK PROTOCOL UNITS 审中-公开
标题翻译：生成网络协议单位的技术
公开(公告)号：WO2007134106A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/068563
申请日：2007-05-09
申请人： INTEL CORPORATION , CORNETT, Linden , KING, Steven , SEN, Sujoy , SARANGAM, Parthasarathy , BERRY, Frank
发明人： CORNETT, Linden , KING, Steven , SEN, Sujoy , SARANGAM, Parthasarathy , BERRY, Frank
CPC分类号： H04L67/1097 , H04L49/90 , H04L49/901 , H04L69/16 , H04L69/161 , H04L69/22
摘要： A first logic offloads some network protocol unit formation tasks to a second logic. The first logic may request that data be transmitted using a Direct Data Placement (DDP) compatible network protocol unit. The first logic may provide the data as well as other information relevant to forming the DDP compatible network protocol unit. The second logic may form portions of the DDP compatible network protocol unit using the data and the provided information.
摘要翻译：第一个逻辑将一些网络协议单元形成任务卸载到第二个逻辑。第一逻辑可以请求使用直接数据放置（DDP）兼容的网络协议单元发送数据。第一逻辑可以提供数据以及与形成DDP兼容的网络协议单元相关的其他信息。第二逻辑可以使用数据和所提供的信息形成DDP兼容网络协议单元的部分。

2. 发明申请

WO2008063826A1 TECHNIQUES TO PROCESS RECEIVED NETWORK PROTOCOL UNITS 审中-公开
标题翻译：处理接收到的网络协议单位的技术
公开(公告)号：WO2008063826A1
公开(公告)日：2008-05-29
申请号：PCT/US2007/082914
申请日：2007-10-30
申请人： INTEL CORPORATION , SARANGAM, Parthasarathy , SEN, Sujoy , CORNETT, Linden
发明人： SARANGAM, Parthasarathy , SEN, Sujoy , CORNETT, Linden
IPC分类号： G06F15/16 , G06F15/173 , H04L12/56
CPC分类号： H04L69/16 , H04L69/161
摘要： Techniques are described that can be used to support integrity validation of protocol data units. An iSCSI compatible logic may establish a memory region to store a header portion of the protocol data unit. In some implementations, the iSCSI compatible logic may read the header and determine a size of a second memory region to store a payload portion of the protocol data unit. In some implementations, the iSCSI compatible logic may set the second memory region as a maximum possible size of the payload portion. TCP compatible logic may include the capability to validate an integrity of the header or data portions of the protocol data unit. TCP compatible logic may request data mover logic to determine an integrity validation value for a header and/or data portion of the protocol data unit in the process of copying the protocol data unit to among the memory region or the second memory region. TCP compatible logic may compare the determined integrity validation value with an integrity validation value included with the protocol data unit.
摘要翻译：描述了可用于支持协议数据单元的完整性验证的技术。 iSCSI兼容逻辑可以建立存储区域以存储协议数据单元的报头部分。在一些实现中，iSCSI兼容逻辑可以读取头部并且确定第二存储器区域的大小以存储协议数据单元的有效载荷部分。在一些实现中，iSCSI兼容逻辑可以将第二存储器区域设置为有效载荷部分的最大可能大小。 TCP兼容逻辑可以包括验证协议数据单元的报头或数据部分的完整性的能力。 TCP兼容逻辑可以在将协议数据单元复制到存储器区域或第二存储器区域的过程中请求数据移动器逻辑来确定协议数据单元的报头和/或数据部分的完整性验证值。 TCP兼容逻辑可以将确定的完整性验证值与协议数据单元所包含的完整性验证值进行比较。

3. 发明申请

WO2013165410A1 PACKET PROCESSING OF DATA USING MULTIPLE MEDIA ACCESS CONTROLLERS 审中-公开
标题翻译：使用多媒体访问控制器的数据分组处理
公开(公告)号：WO2013165410A1
公开(公告)日：2013-11-07
申请号：PCT/US2012/036108
申请日：2012-05-02
申请人： INTEL CORPORATION , GASPARAKIS, Iosif , WASKIEWICZ JR, Peter P. , GANGA, Ilango S. , HULETT, Terry V. , SARANGAM, Parthasarathy
发明人： GASPARAKIS, Iosif , WASKIEWICZ JR, Peter P. , GANGA, Ilango S. , HULETT, Terry V. , SARANGAM, Parthasarathy
IPC分类号： H04L12/56 , H04L29/12 , H04L29/10
CPC分类号： H04L67/02 , G06F9/45533 , H04L69/321
摘要： Examples are disclosed for a device having at least two media access controllers. In some examples, a first media access controller may be coupled to a host computing device. A second media access controller may be coupled to one or more processor circuits arranged to perform packet processing of data payloads for one or more data frames forwarded through the first media access controller and/or forwarded through the second media access controller. The first media access controller may be coupled to the second media access controller via a communication link. Other examples are described and claimed.
摘要翻译：公开了具有至少两个媒体访问控制器的设备的示例。在一些示例中，第一媒体访问控制器可以耦合到主计算设备。第二媒体接入控制器可以耦合到一个或多个处理器电路，其被布置为对通过第一媒体接入控制器转发的一个或多个数据帧执行数据有效载荷的分组处理和/或通过第二媒体接入控制器转发。第一媒体接入控制器可以经由通信链路耦合到第二媒体接入控制器。其他的例子被描述和要求保护。

4. 发明申请

WO2013081620A1 SERVER INCLUDING SWITCH CIRCUITRY 审中-公开
标题翻译：服务器包括开关电路
公开(公告)号：WO2013081620A1
公开(公告)日：2013-06-06
申请号：PCT/US2011/062912
申请日：2011-12-01
申请人： INTEL CORPORATION , VASUDEVAN, Anil , SARANGAM, Parthasarathy , GANGA, Ilango S.
发明人： VASUDEVAN, Anil , SARANGAM, Parthasarathy , GANGA, Ilango S.
IPC分类号： G06F13/14 , G06F15/16 , H04L29/02
CPC分类号： H04L41/04 , G06F13/385
摘要： An embodiment may include at least one server processor that may control, at least in part, server switch circuitry data and control plane processing. The at least one processor may include at least one cache memory that is capable of being involved in at least one data transfer that involves at least one component of the server. The at least one data transfer may be carried out in a manner that by-passes involvement of server system memory. The switch circuitry may be communicatively coupled to the at least one processor and to at least one node via communication links. The at least one processor may select, at least in part, at least one communication protocol to be used by the links. The switch circuitry may forward, at least in part, via at least one of the links at least one received packet. Many modifications are possible.
摘要翻译：一个实施例可以包括至少一个可以至少部分地控制服务器交换机电路数据和控制平面处理的服务器处理器。所述至少一个处理器可以包括至少一个高速缓存存储器，其能够涉及涉及服务器的至少一个组件的至少一个数据传输。所述至少一个数据传送可以以服务器系统存储器的旁路方式进行。开关电路可以经由通信链路通信地耦合到至少一个处理器和至少一个节点。至少一个处理器可以至少部分地选择要由链路使用的至少一个通信协议。至少部分地，交换机电路经由至少一个链路至少一个接收的分组转发。许多修改是可能的。

5. 发明申请

WO2011078861A1 A COMPUTER PLATFORM PROVIDING HARDWARE SUPPORT FOR VIRTUAL INLINE APPLIANCES AND VIRTUAL MACHINES 审中-公开
标题翻译：为虚拟在线电器和虚拟机提供硬件支持的计算机平台
公开(公告)号：WO2011078861A1
公开(公告)日：2011-06-30
申请号：PCT/US2009/069386
申请日：2009-12-23
申请人： INTEL CORPORATION , SAHITA, Ravi, L. , RAMANUJAN, Raj, K. , RAGHUNATH, Arun , ZINATY, Amir , SARANGAM, Parthasarathy
发明人： SAHITA, Ravi, L. , RAMANUJAN, Raj, K. , RAGHUNATH, Arun , ZINATY, Amir , SARANGAM, Parthasarathy
IPC分类号： G06F13/14 , G06F15/16 , G06F9/44 , G06F3/00
CPC分类号： G06F9/45558 , G06F2009/4557 , G06F2009/45595 , H04L69/12 , H04L69/22 , H04L69/324
摘要： A computer platform may support hardware assisted packet handling to efficiently filter and route packets in an ordered sequence through a virtual network of inline appliances and virtual machines via network interface card (NIC) and other platform hardware. The hardware may add, update, and parse tags representing routing action into packets. The computer platform may support hardware assisted inter-VM communication without requiring additional processor cycles to switch packets between inline appliances in single root I/O virtualized (SR-IOV) and multiple root I/O virtualized (MR-IOV) scenarios. The computer platform may support hardware assisted VM migration technique to reduce the complexity and software overheads involved in migrating a running virtual machine from one platform to the other.
摘要翻译：计算机平台可以支持硬件辅助分组处理，以通过网络接口卡（NIC）和其他平台硬件通过内联设备和虚拟机的虚拟网络以有序序列有效地过滤和路由分组。硬件可以将表示路由动作的标签添加，更新和解析成分组。计算机平台可以支持硬件辅助的VM间通信，而不需要额外的处理器周期来在单根I / O虚拟化（SR-IOV）和多根I / O虚拟化（MR-IOV）场景中的内联设备之间切换数据包。计算机平台可以支持硬件辅助的VM迁移技术，以减少将正在运行的虚拟机从一个平台迁移到另一个平台所涉及的复杂性和软件开销。

6. 发明申请

WO2021086457A1 EVOLVING HYPERVISOR PASS-THROUGH DEVICE TO BE CONSISTENTLY PLATFORM-INDEPENDENT BY MEDIATED-DEVICE IN USER SPACE (MUSE) 审中-公开
公开(公告)号：WO2021086457A1
公开(公告)日：2021-05-06
申请号：PCT/US2020/041883
申请日：2020-07-14
申请人： LU, Xiuchun , LIANG, Cunming , HE, Shaopeng , JANI, Nrupal , JAIN, Anjali , VERPLANKE, Edwin , SARANGAM, Parthasarathy , YAN, Zhirun
发明人： LU, Xiuchun , LIANG, Cunming , HE, Shaopeng , JANI, Nrupal , JAIN, Anjali , VERPLANKE, Edwin , SARANGAM, Parthasarathy , YAN, Zhirun
IPC分类号： G06F9/455 , G06F13/28 , H04L12/24
摘要： Methods and apparatus for evolving hypervisor pass-through devices supporting platform independence through a core solution called MUSE (Mdev in User SpacE) that allows mediated pass-through device being served by software running in user space. The MUSE architecture supports platform hardware independence while providing pass-through performance similar to hardware-specific solutions and providing enhanced performance in virtualized environments using existing software components, including various operating systems and associated libraries for implementing SDN (Software Defined Networking) and VNF (Virtualized Network Function).

7. 发明申请

WO2019089131A1 TECHNOLOGIES FOR PROGRAMMING FLEXIBLE ACCELERATED NETWORK PIPELINE USING EBPF 审中-公开
公开(公告)号：WO2019089131A1
公开(公告)日：2019-05-09
申请号：PCT/US2018/050204
申请日：2018-09-10
申请人： INTEL CORPORATION
发明人： WASKIEWICZ, Peter P. , JAIN, Anjali Singhai , PARIKH, Neerav , SARANGAM, Parthasarathy
IPC分类号： G06F9/445 , G06F9/448 , G06F8/41
摘要： Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file. Other embodiments are described and claimed.

8. 发明申请

WO2017131874A1 ENHANCED VIRTUAL FUNCTION CAPABILITIES IN A VIRTUALIZED NETWORK ENVIRONMENT 审中-公开
标题翻译：虚拟网络环境下增强的虚函数能力
公开(公告)号：WO2017131874A1
公开(公告)日：2017-08-03
申请号：PCT/US2016/066149
申请日：2016-12-12
申请人： INTEL CORPORATION
发明人： PALERMO, Stephen, T. , DUBAL, Scott, P. , COOPER, Trevor , JAIN, Anjali S. , GASPARAKIS, Iosif , TSAI, Jr-Shian , BURSELL, Mike , GANESH, Pradeepsunder , SARANGAM, Parthasarathy , BRANDEBURG, Jesse C,
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F9/5011 , G06F2009/45583 , G06F2009/45595
摘要： The present disclosure is directed to enhanced virtual function capabilities in a virtualized network environment. In general, devices may comprise physical and virtualized resources. The physical resources may comprise at least a network adaptor that may handle incoming data from a network and outgoing data to the network. The virtualized resources may comprise at least one virtual machine (VM) and a corresponding interface. The corresponding interface may be one of a physical interface, a virtual interface or a "super" virtual interface. The physical interface may provide a first set of capabilities allowing the VM to access (e.g., control) at least the network adaptor. The virtual interface may provide a second set of capabilities that is a subset of the first set. The super virtual interface may provide a third set of capabilities including the second set of capabilities and at least one additional capability from the first set of capabilities.
摘要翻译：本公开针对虚拟化网络环境中的增强的虚拟功能能力。通常，设备可以包括物理和虚拟化资源。物理资源可以至少包括可以处理来自网络的输入数据和输出到网络的数据的网络适配器。虚拟化资源可以包括至少一个虚拟机（VM）和对应的接口。相应的接口可以是物理接口，虚拟接口或“超级”接口之一。虚拟界面。物理接口可以提供允许VM访问（例如，控制）至少网络适配器的第一组能力。虚拟接口可以提供作为第一组的子集的第二组能力。超级虚拟接口可以提供包括第二组能力和来自第一组能力的至少一个附加能力的第三组能力。

9. 发明申请

WO2022271239A1 QUEUE SCALING BASED, AT LEAST, IN PART, ON PROCESSING LOAD 审中-公开
公开(公告)号：WO2022271239A1
公开(公告)日：2022-12-29
申请号：PCT/US2022/021809
申请日：2022-03-24
申请人： INTEL CORPORATION
发明人： VASUDEVAN, Anil , SAMUDRALA, Sridhar , PATIL, Kiran , NAMBIAR, Amritha , SARANGAM, Parthasarathy
IPC分类号： G06F9/48 , G06F9/52 , G06F2209/5018 , G06F9/4881 , G06F9/5083 , G06F9/526
摘要： Examples described herein relate to one or more processors that execute a number of polling threads based on a number of queue identifiers, wherein at least one of the queue identifiers is associated with one or more queues. In some examples, the one or more processors selectively adjust a number of queue identifiers based on a load level of a queue. In some examples, the load level of a queue indicates a number of packets processed per unit of time. In some examples, the number of queue identifiers is no more than a number of configured queues. In some examples, the one or more queues are associated with a queue exclusively allocated to a thread for reading or writing.

10. 发明申请

WO2020247042A1 NETWORK INTERFACE FOR DATA TRANSPORT IN HETEROGENEOUS COMPUTING ENVIRONMENTS 审中-公开
公开(公告)号：WO2020247042A1
公开(公告)日：2020-12-10
申请号：PCT/US2020/023934
申请日：2020-03-20
申请人： INTEL CORPORATION
发明人： MAROLIA, Pratik M. , SANKARAN, Rajesh M. , RAJ, Ashok , JANI, Nrupal , SARANGAM, Parthasarathy , SHARP, Robert O.
IPC分类号： H04L12/747 , G06F13/28 , H04L12/861 , G06F12/1081 , H04L12/773
摘要： A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

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