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1. 发明申请

WO2015050557A1 TECHNIQUES FOR HETEROGENEOUS CORE ASSIGNMENT 审中-公开
标题翻译：异质核心分配技术
公开(公告)号：WO2015050557A1
公开(公告)日：2015-04-09
申请号：PCT/US2013/063399
申请日：2013-10-04
申请人： INTEL CORPORATION , BARIK, Rajkishore , LEWIS, Brian T. , SHPEISMAN, Tatiana
发明人： BARIK, Rajkishore , LEWIS, Brian T. , SHPEISMAN, Tatiana
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/30145 , G06F1/263 , G06F8/451 , G06F9/3822 , G06F9/5094 , G06F2209/508 , Y02D10/22
摘要： Various embodiments are generally directed to techniques for assigning instances of blocks of instructions of a routine to one of multiple types of core of a heterogeneous set of cores of a processor component. An apparatus to select types of cores includes a processor component; a core selection component for execution by the processor component to select a core of multiple cores to execute an initial subset of multiple instances of an instruction block in parallel based on characteristics of instructions of the instruction block, and to select a core of the multiple cores to execute remaining instances of the multiple instances of the instruction block in parallel based on characteristics of execution of the initial subset stored in an execution database; and a monitoring component for execution by the processor component to record the characteristics of execution of the initial subset in the execution database. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及用于将例程的指令块的实例分配给处理器组件的异构集群核心的多种类型的核心之一的技术。选择核心类型的装置包括处理器组件; 核心选择部件，用于由处理器部件执行以选择多个核的核心，以基于指令块的指令的特性并行地执行指令块的多个实例的初始子集，并且选择多个核心的核心基于存储在执行数据库中的初始子集的执行特性来并行执行指令块的多个实例的剩余实例; 以及用于由处理器组件执行以在执行数据库中记录初始子集的执行特性的监视组件。描述和要求保护其他实施例。

2. 发明申请

WO2014107143A2 METHOD, APPARATUS, AND SYSTEM FOR ADAPTIVE THREAD SCHEDULING IN TRANSACTIONAL MEMORY SYSTEMS 审中-公开
标题翻译：在事务存储器系统中用于自适应线程调度的方法，装置和系统
公开(公告)号：WO2014107143A2
公开(公告)日：2014-07-10
申请号：PCT/US2012/059204
申请日：2012-10-08
申请人： INTEL CORPORATION , LEWIS, Brian T. , SAHA, Bratin
发明人： LEWIS, Brian T. , SAHA, Bratin
CPC分类号： G06F9/4843 , G06F9/467 , G06F9/4881
摘要： An apparatus and method is described herein for adaptive thread scheduling in a transactional memory environment. A number of conflicts in a thread over time are tracked. And if the conflicts exceed a threshold, the thread may be delayed (adaptively scheduled) to avoid conflicts between competing threads. Moreover, a more complex version may track a number of transaction aborts within a first thread that are caused by a second thread over a period, as well as a total number of transactions executed by the first thread over the period. From the tracking, a conflict ratio is determined for the first thread with regard to the second thread. And when the first thread is to be scheduled, it may be delayed if the second thread is running and the conflict ratio is over a conflict ratio threshold.
摘要翻译：这里描述了用于事务存储器环境中的自适应线程调度的装置和方法。跟踪随时间推移的线索中的多个冲突。如果冲突超过阈值，线程可能会延迟（自适应调度）以避免竞争线程之间的冲突。此外，更复杂的版本可以追踪由第二线程在一段时间内引起的第一线程内的多个事务中止以及第一线程在该时间段内执行的事务的总数。从跟踪中，针对第二线程针对第一线程确定冲突比率。当第一个线程被调度时，如果第二个线程正在运行并且冲突比率超过冲突比率阈值，它可能会延迟。

3. 发明申请

WO2016099820A1 IMPROVED FUNCTION CALLBACK MECHANISM BETWEEN A CENTRAL PROCESSING UNIT (CPU) AND AN AUXILIARY PROCESSOR 审中-公开
标题翻译：中央处理单元（CPU）与辅助处理器之间的改进功能调用机制
公开(公告)号：WO2016099820A1
公开(公告)日：2016-06-23
申请号：PCT/US2015/062302
申请日：2015-11-24
申请人： INTEL CORPORATION
发明人： LEWIS, Brian T. , BARIK, Rajkishore , SHPEISMAN, Tatiana
IPC分类号： G06F13/12 , G06F13/16
CPC分类号： G06F9/544 , G06T1/20
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.
摘要翻译：通常，本公开提供了用于在第一处理器（例如，GPU）和第二处理器（例如，CPU）之间实现功能回调请求的系统，设备，方法和计算机可读介质。该系统可以包括耦合到第一和第二处理器的共享虚拟存储器（SVM），所述SVM被配置为存储至少一个双端队列（Deque）。第一处理器的执行单元（EU）可以与第一个Deques相关联，并被配置为将回调请求推送到第一个Deque。在第二处理器上执行的请求处理程序线程可以被配置为：从第一Deque弹出一个回调请求; 执行弹出的回调请求指定的功能; 并响应功能的完成向EU产生完成信号。

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