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1. 发明申请

WO2017052930A1 ASYNCHRONOUS ON-DIE EYE SCOPE 审中-公开
标题翻译：非同寻常的眼科眼睛范围
公开(公告)号：WO2017052930A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/048464
申请日：2016-08-24
申请人： INTEL CORPORATION
发明人： XU, Mingming , GIACONI, Stefano , WANG, Wei
IPC分类号： G01R31/317 , G01R13/02
CPC分类号： G06K9/0053 , G01R13/02 , G06K9/00503 , G06K9/00557 , G06K9/00604
摘要： Some embodiments include apparatuses and methods having a receiver unit included in a die and a measurement unit included in the die. The receiver unit includes a sampler to sample a first signal based on timing of a first clock signal to generate a second signal. The measurement unit is arranged to sample the first signal based on timing of a second clock signal to provide information for generation of a graph presenting an eye scan of the first signal. The second clock signal has a frequency asynchronous with a frequency of the first clock signal.
摘要翻译：一些实施例包括具有包括在管芯中的接收器单元和包括在管芯中的测量单元的装置和方法。接收器单元包括采样器，用于基于第一时钟信号的定时对第一信号进行采样以产生第二信号。测量单元被布置为基于第二时钟信号的定时对第一信号进行采样，以提供用于生成呈现第一信号的眼睛扫描的图形的信息。第二时钟信号具有与第一时钟信号的频率异步的频率。

2. 发明申请

WO2020123020A1 CLOCK RECOVERY CIRCUIT AND METHOD OF OPERATING SAME 审中-公开
公开(公告)号：WO2020123020A1
公开(公告)日：2020-06-18
申请号：PCT/US2019/055632
申请日：2019-10-10
申请人： INTEL CORPORATION
发明人： DUDULWAR, Pankaj , VERMA, Mohit , SONG, Hongjiang , XU, Mingming
IPC分类号： H04L7/033 , H04L7/00
摘要： Techniques and mechanisms for a clock recovery circuit to generate a cyclical signal based on data signals which are susceptible to circuit switching jitter. In an embodiment, a clock recovery circuit comprises switch circuitry which receives a first signal representing a logical combination of multiple pulsed signals (which, in turn, are each based on a different respective differential data signal). The switch circuitry provides to latch circuitry of the clock recovery circuit a second signal based on the first signal. The latch circuitry generates a cyclical signal based on the second signal, and transitions the switch circuitry between an open-circuit state and a closed-circuit state. In another embodiment, the latch circuitry implements a predetermined and configurable time period between a transition of the cyclical signal and a next subsequent logic state transition of the cyclical signal.

3. 发明申请

WO2015099919A1 PHASE ADJUSTMENT CIRCUIT FOR CLOCK AND DATA RECOVERY CIRCUIT 审中-公开
标题翻译：用于时钟和数据恢复电路的相位调整电路
公开(公告)号：WO2015099919A1
公开(公告)日：2015-07-02
申请号：PCT/US2014/066897
申请日：2014-11-21
申请人： INTEL CORPORATION
发明人： GIACONI, Stefano , XU, Mingming
IPC分类号： H04L7/033
CPC分类号： H04L25/03057 , H04L7/0041 , H04L7/0058 , H04L7/033 , H04L7/0331 , H04L7/0332 , H04L7/0334 , H04L25/03025 , H04L2025/03598
摘要： Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.
摘要翻译：描述了用于时钟和数据恢复电路（CDR）的相位调整电路。系统和装置可以包括用于接收串行数据信号的输入端，边缘数据抽头以对串行数据信号中的过渡边缘采样以产生数据边缘检测信号; CDR电路，包括用于接收串行数据信号的相位检测器和数据边缘检测信号，并输出指示串行数据信号和数据边缘检测信号之间的相位差的相位超前/滞后信号，以及相位调整电路，以产生相位超前/滞后调整数据。 CDR电路至少部分地基于由相位超前/滞后调整数据调整的相位超前/滞后信号来输出恢复的时钟信号。

4. 发明申请

WO2014158482A1 POWER AND AREA EFFICIENT RECEIVER EQUALIZATION ARCHITECTURE WITH RELAXED DFE TIMING CONSTRAINT 审中-公开
标题翻译：功率和面积有效的接收器均衡架构与松弛的DFE时序约束
公开(公告)号：WO2014158482A1
公开(公告)日：2014-10-02
申请号：PCT/US2014/017221
申请日：2014-02-19
申请人： INTEL CORPORATION
发明人： XU, Mingming , GIACONI, Stefano
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L2025/03471
摘要： An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).
摘要翻译：示例性接收机均衡器包括耦合到夏季的第一判决反馈均衡器（DFE）采样器，所述第一DFE用于锁存所述夏季的均衡输出。第一分支包括耦合到第一DFE采样器的第二DFE采样器，第二DFE采样器锁存第一DFE采样器的输出。第一分支包括耦合到第二DFE采样器的第三DFE采样器，第三DFE用于锁存第二DFE采样器的输出。夏天耦合到第一分支的第一，第二和第三DFE采样器，夏天将所述DFE采样器的输出，接收信号和来自一个或多个其他分支的均衡输出进行积分，其中积分发生在多个的单位间隔（UI）。

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