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1. 发明申请

WO2011078861A1 A COMPUTER PLATFORM PROVIDING HARDWARE SUPPORT FOR VIRTUAL INLINE APPLIANCES AND VIRTUAL MACHINES 审中-公开
标题翻译：为虚拟在线电器和虚拟机提供硬件支持的计算机平台
公开(公告)号：WO2011078861A1
公开(公告)日：2011-06-30
申请号：PCT/US2009/069386
申请日：2009-12-23
申请人： INTEL CORPORATION , SAHITA, Ravi, L. , RAMANUJAN, Raj, K. , RAGHUNATH, Arun , ZINATY, Amir , SARANGAM, Parthasarathy
发明人： SAHITA, Ravi, L. , RAMANUJAN, Raj, K. , RAGHUNATH, Arun , ZINATY, Amir , SARANGAM, Parthasarathy
IPC分类号： G06F13/14 , G06F15/16 , G06F9/44 , G06F3/00
CPC分类号： G06F9/45558 , G06F2009/4557 , G06F2009/45595 , H04L69/12 , H04L69/22 , H04L69/324
摘要： A computer platform may support hardware assisted packet handling to efficiently filter and route packets in an ordered sequence through a virtual network of inline appliances and virtual machines via network interface card (NIC) and other platform hardware. The hardware may add, update, and parse tags representing routing action into packets. The computer platform may support hardware assisted inter-VM communication without requiring additional processor cycles to switch packets between inline appliances in single root I/O virtualized (SR-IOV) and multiple root I/O virtualized (MR-IOV) scenarios. The computer platform may support hardware assisted VM migration technique to reduce the complexity and software overheads involved in migrating a running virtual machine from one platform to the other.
摘要翻译：计算机平台可以支持硬件辅助分组处理，以通过网络接口卡（NIC）和其他平台硬件通过内联设备和虚拟机的虚拟网络以有序序列有效地过滤和路由分组。硬件可以将表示路由动作的标签添加，更新和解析成分组。计算机平台可以支持硬件辅助的VM间通信，而不需要额外的处理器周期来在单根I / O虚拟化（SR-IOV）和多根I / O虚拟化（MR-IOV）场景中的内联设备之间切换数据包。计算机平台可以支持硬件辅助的VM迁移技术，以减少将正在运行的虚拟机从一个平台迁移到另一个平台所涉及的复杂性和软件开销。

2. 发明申请

WO2017112315A1 NON-TRACKED CONTROL TRANSFERS WITHIN CONTROL TRANSFER ENFORCEMENT 审中-公开
标题翻译：非追踪控制权转让的控制权转移执行
公开(公告)号：WO2017112315A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063665
申请日：2016-11-23
申请人： INTEL CORPORATION
发明人： SHANBHOGUE, Vedvyas , SAHITA, Ravi, L. , GUPTA, Deepak, K.
IPC分类号： G06F21/54 , G06F21/50
CPC分类号： G06F9/3861 , G06F9/3005 , G06F9/30054 , G06F9/30076 , G06F21/123 , G06F21/125
摘要： A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state; responsive to executing a control transfer instruction having a pre-defined subcode, remain in the first execution state; responsive to executing a control transfer instruction not having the pre-defined subcode, transition into a second execution state; and responsive to determining, in the second execution state, that a next instruction to be executed differs from an ENDBRANCH instruction, raise an execution exception.
摘要翻译：处理器包括执行单元和可操作地耦合到执行单元的处理逻辑，处理逻辑用于：进入第一执行状态; 响应于执行具有预定子代码的控制传送指令，保持在第一执行状态; 响应于执行不具有预定子码的控制传送指令，转换到第二执行状态; 并响应于在第二执行状态中确定要执行的下一条指令与ENDBRANCH指令不同，引发执行异常。

3. 发明申请

WO2007111662A2 METHOD, APPARATUS AND SYSTEM FOR PERFORMING ACCESS CONTROL AND INTRUSION DETECTION ON ENCRYPTED DATA 审中-公开
标题翻译：用于对加密数据执行访问控制和侵入检测的方法，装置和系统
公开(公告)号：WO2007111662A2
公开(公告)日：2007-10-04
申请号：PCT/US2006/047905
申请日：2006-12-14
申请人： INTEL CORPORATION , KOHLENBERG, Tobias, M. , SAHITA, Ravi, L.
发明人： KOHLENBERG, Tobias, M. , SAHITA, Ravi, L.
CPC分类号： H04L63/1416
摘要： A method, apparatus and system enable access control and intrusion detection on encrypted data. Specifically, application data on a node may be routed to a partition on the host. The partition may utilize Direct Memory Access ("DMA") to access session key stored in a host OS. The partition may thereafter utilize the session key to perform intrusion detection on encrypted data from the application.
摘要翻译：一种方法，装置和系统启用对加密数据的访问控制和入侵检测。具体来说，节点上的应用数据可以被路由到主机上的分区。分区可以利用直接存储器访问（“DMA”）来访问存储在主机OS中的会话密钥。该分区此后可以利用会话密钥对来自应用的加密数据执行入侵检测。

4. 发明申请

WO2017123390A1 INTERRUPTS BETWEEN VIRTUAL MACHINES 审中-公开
标题翻译：虚拟机之间的中断
公开(公告)号：WO2017123390A1
公开(公告)日：2017-07-20
申请号：PCT/US2016/067849
申请日：2016-12-20
申请人： INTEL CORPORATION
发明人： TSAI, Jr-Shian , SAHITA, Ravi, L. , ERGIN, Mesut, A. , SANKARAN, Rajesh, M. , NEIGER, Gilbert , NAKAJIMA, Jun , VERPLANKE, Edwin , HUNTLEY, Barry, E. , TAI, Tsung-Yuan, C.
IPC分类号： G06F9/32 , G06F9/30
CPC分类号： G06F13/24 , G06F9/45558 , G06F2009/45575 , G06F2009/45579
摘要： Embodiments of an invention interrupts between virtual machines are disclosed. In an embodiment, a processor includes an instruction unit and an execution unit, both implemented at least partially in hardware of the processor. The instruction unit is to receive an instruction to send an interrupt to a target virtual machine. The execution unit is to execute the instruction on a sending virtual machine without exiting the sending virtual machine. Execution of the instruction includes using a handle specified by the instruction to find a posted interrupt descriptor.
摘要翻译：公开了虚拟机之间的本发明中断的实施例。在一个实施例中，处理器包括指令单元和执行单元，二者至少部分地以处理器的硬件实现。指令单元将接收向目标虚拟机发送中断的指令。执行单元将在不退出发送虚拟机的情况下在发送虚拟机上执行该指令。执行指令包括使用指令指定的句柄来查找发布的中断描述符。

5. 发明申请

WO2016105562A1 MEMORY PROTECTION WITH NON-READABLE PAGES 审中-公开
标题翻译：具有不可读页的记忆保护
公开(公告)号：WO2016105562A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/000457
申请日：2015-12-26
申请人： INTEL CORPORATION
发明人： BACHWANI, Rekha, N. , SAHITA, Ravi, L. , DURHAM, David, M.
IPC分类号： G06F12/00
CPC分类号： G06F12/14 , G06F12/10 , G06F12/1408 , G06F12/1441 , G06F2212/1052 , G06F2212/657
摘要： A method includes, in various implementations, regulating a memory region for execute- only access, storing a set of instructions in the memory region, executing an early instruction among the set of instructions, and executing a set of subsequent instructions among the instructions. The early instruction loads a secret value into a volatile register. A correct execution of the subsequent instructions depends on the secret value being loaded into the volatile register. A system includes, in various implementations, a memory and a processor with one or more volatile registers. The processor regulates access to portions of the memory. The processor can load a secret value into the volatile register in response to executing a program stored in an execute-only portion of the memory. The processor is configured to lose, in response to an asynchronous event, information loaded in the volatile registers.
摘要翻译：一种方法包括在各种实施方式中调节用于仅执行访问的存储器区域，将一组指令存储在存储器区域中，在该组指令之间执行早期指令，以及在指令之间执行一组后续指令。早期指令将一个秘密值加载到易失性寄存器中。后续指令的正确执行取决于加载到易失性寄存器中的秘密值。在各种实现中，系统包括具有一个或多个易失性寄存器的存储器和处理器。处理器调节对存储器部分的访问。响应于执行存储在存储器的仅执行部分中的程序，处理器可以将秘密值加载到易失性寄存器中。处理器被配置为响应于异步事件丢失加载在易失性寄存器中的信息。

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