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1. 发明申请

WO2018009296A1 READ FROM MEMORY INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS, THAT DO NOT TAKE EXCEPTION ON DEFECTIVE DATA 审中-公开
标题翻译：从存储器指令，处理器，方法和系统中读取，不排除有缺陷的数据
公开(公告)号：WO2018009296A1
公开(公告)日：2018-01-11
申请号：PCT/US2017/036040
申请日：2017-06-06
申请人： INTEL CORPORATION
发明人： RAJ, Ashok , GABOR, Ron , SHAFI, Hisham , GHETIE, Sergiu , KUMAR, Mohan J. , YIGZAW, Theodros , JAYAKUMAR, Sarathy , UPASANI, Neeraj S.
IPC分类号： G06F13/16 , G06F11/07
摘要： A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
摘要翻译：一方面的处理器包括解码单元，以解码来自存储器指令的读取。从存储器指令读取的是指示源存储器操作数和目标存储位置。处理器还包括与解码单元耦合的执行单元。响应于从存储器指令中读取，执行单元从源存储器操作数读取数据，在数据有缺陷时将有缺陷数据的指示存储在架构上可见的存储位置中，并且从存储器完成读取的执行指令，而不会导致异常情况，当数据有缺陷时。披露了其他处理器，方法，系统和指令。

2. 发明申请

WO2016153586A1 BYTE LEVEL GRANULARITY BUFFER OVERFLOW DETECTION FOR MEMORY CORRUPTION DETECTION ARCHITECTURES 审中-公开
标题翻译：用于存储器腐蚀检测结构的BYTE LEVEL GRANULARITY BUFFER OVERFLOW DETECTION
公开(公告)号：WO2016153586A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/014180
申请日：2016-01-20
申请人： INTEL CORPORATION
发明人： STARK, Tomer , TAL, Ady , GABOR, Ron , NUZMAN, Jospeh
IPC分类号： G06F11/07 , G06F12/14 , G06F12/02
CPC分类号： G06F11/0751 , G06F11/073
摘要： Memory corruption detection technologies are described. A processor can include a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table. The processor can also include processor core coupled to the memory. The processor core can receive, from an application, a memory access request to access data of one or more contiguous memory blocks in a memory object of the memory. The processor core can also retrieve data stored in the one or more contiguous memory blocks based on the location indicated by the pointer. The processor core can also retrieve, from the MCD table, allocation information associated with the one or more contiguous memory blocks. The processor core can also send, to the application, a fault message when a fault event associated with the retrieved data occurs based on the allocation information
摘要翻译：描述内存损坏检测技术。处理器可以包括用于存储来自应用程序的数据的存储器，其中存储器包括存储器损坏检测（MCD）表。处理器还可以包括耦合到存储器的处理器核心。处理器核可以从应用程序接收存储器访问请求以访问存储器的存储器对象中的一个或多个连续的存储器块的数据。处理器核还可以基于指针指示的位置来检索存储在一个或多个连续存储器块中的数据。处理器核心还可以从MCD表中检索与一个或多个连续存储器块相关联的分配信息。当与检索到的数据相关联的故障事件基于分配信息发生时，处理器核心还可以向应用发送故障消息

3. 发明申请

WO2017074615A1 INTERFACING WITH BLOCK-BASED STORAGE IN A PROCESSOR 审中-公开
标题翻译：在处理器中与基于块的存储进行接口
公开(公告)号：WO2017074615A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/053094
申请日：2016-09-22
申请人： INTEL CORPORATION
发明人： YIGZAW, Theodros , KUMAR, Mohan J. , SHAFI, Hisham , GABOR, Ron , RAJ, Ashok
IPC分类号： G06F9/38 , G06F11/07
CPC分类号： G06F11/079 , G06F9/3004 , G06F9/30101 , G06F9/3016 , G06F11/0721 , G06F11/0784 , G06F11/0787 , G06F11/0793 , G06F12/00
摘要： In one embodiment, a processor includes a core having a fetch unit to fetch instructions, a decode unit to decode the instructions, and one or more execution units to execute the instructions. The core may further include: a first pair of block address range registers to store a start location and an end location of a block range within a non-volatile block storage coupled to the processor; and a block status storage to store an error indicator responsive to an occurrence of an error within the block range during a block operation. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括具有用于提取指令的提取单元的核心，用于解码指令的解码单元以及用于执行指令的一个或多个执行单元。内核还可以包括：第一对块地址范围寄存器，用于在耦合到处理器的非易失性块存储器内存储块范围的开始位置和结束位置; 以及块状态存储器，用于响应块操作期间在块范围内发生错误而存储错误指示符。描述并要求保护其他实施例。

4. 发明申请

WO2018009289A1 ENHANCED ADDRESS SPACE LAYOUT RANDOMIZATION 审中-公开
标题翻译：增强的地址空间布局随机化
公开(公告)号：WO2018009289A1
公开(公告)日：2018-01-11
申请号：PCT/US2017/035784
申请日：2017-06-02
申请人： INTEL CORPORATION
发明人： STARK, Tomer , GABOR, Ron , NUZMAN, Joseph
IPC分类号： G06F21/12 , G06F17/30
CPC分类号： G06F11/073 , G06F11/0727 , G06F12/0623 , G06F12/14 , G06F2212/1052 , G06F2212/657
摘要： One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.
摘要翻译：一个实施例提供了一种装置。该装置包括线性地址空间，元数据逻辑和增强型地址空间布局随机化（ASLR）逻辑。线性地址空间包括元数据数据结构。元数据逻辑将生成元数据值。增强型ASLR逻辑将元数据值和线性地址组合为地址指针，并且将元数据值存储到线性地址的至少一部分指向的位置处的元数据数据结构。地址指针对应于增强地址空间中的表观地址。增强地址空间的大小大于线性地址空间的大小。

5. 发明申请

WO2015048023A1 RECOVERY FROM MULTIPLE DATA ERRORS 审中-公开
标题翻译：从多个数据错误中恢复
公开(公告)号：WO2015048023A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/056993
申请日：2014-09-23
申请人： INTEL CORPORATION
发明人： SADE, Raanan , GABOR, Ron , BUCH, Deep K. , YIGZAW, Theodros , SHWARTSMAN, Stanislav
IPC分类号： G06F11/08 , G06F12/00
CPC分类号： G06F11/073 , G06F11/0793 , G06F11/08
摘要： Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.
摘要翻译：提供了同时处理多个数据错误的机制。处理设备可以确定在存储器位置范围内的存储器位置中是否发生多个数据错误。如果多个存储器位置在存储器位置的范围内，则处理设备可以继续恢复过程。如果多个存储器位置中的一个位于存储器位置的范围之外，则处理设备可以停止恢复过程。

6. 发明申请

WO2012087561A2 SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS 审中-公开
标题翻译：用于硬件和软件系统的系统，设备和方法，用于自动将程序分解成多个并行线程
公开(公告)号：WO2012087561A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/063466
申请日：2011-12-06
申请人： INTEL CORPORATION , SAGER, David J. , SASANKA, Ruchira , GABOR, Ron , RAIKIN, Shlomo , NUZMAN, Joseph , PELED, Leeor , DOMER, Jason A. , KIM, Ho-Seop , WU, Youfeng , YAMADA, Koichi , NGAI, Tin-Fook , CHEN, Howard H. , BOBBA, Jayaram , COOK, Jeffrey J. , SHAIKH, Osmar M. , SRINIVAS, Suresh
发明人： SAGER, David J. , SASANKA, Ruchira , GABOR, Ron , RAIKIN, Shlomo , NUZMAN, Joseph , PELED, Leeor , DOMER, Jason A. , KIM, Ho-Seop , WU, Youfeng , YAMADA, Koichi , NGAI, Tin-Fook , CHEN, Howard H. , BOBBA, Jayaram , COOK, Jeffrey J. , SHAIKH, Osmar M. , SRINIVAS, Suresh
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
摘要翻译：描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。在一些实施例中，系统和装置执行原始代码分解和/或生成的线程执行的方法。

7. 发明申请

WO2007038011A1 REAL-TIME THREADING SERVICE FOR PARTITIONED MULTIPROCESSOR SYSTEMS 审中-公开
标题翻译：用于分散式多处理器系统的实时打线服务
公开(公告)号：WO2007038011A1
公开(公告)日：2007-04-05
申请号：PCT/US2006/035961
申请日：2006-09-12
申请人： INTEL CORPORATION , KULBAK, Yoram , SHAMIA, Doron , RAYNOR, Scott , HELD, Jim , GABOR, Ron
发明人： KULBAK, Yoram , SHAMIA, Doron , RAYNOR, Scott , HELD, Jim , GABOR, Ron
IPC分类号： G06F9/46
CPC分类号： G06F9/4843
摘要： An embodiment of the present invention is a technique to provide a real-time threading service to an application in a multi-core environment. An executive is launched, within a most privilege level of an operating system (OS), on a real-time core in the multi- core environment. The real-time core is sequestered from the OS. A real-time thread is created in a least privilege level on the real-time core for an application using a library. The library is loaded by the application. The real-time thread shares a virtual address space with the application.
摘要翻译：本发明的实施例是一种向多核环境中的应用提供实时线程服务的技术。在多核环境中的实时核心上，一个执行者在操作系统（OS）的最特权级别中启动。实时核心是从操作系统中隔离出来的。在使用库的应用程序的实时内核的最小权限级别中创建实时线程。该库由应用程序加载。实时线程与应用程序共享虚拟地址空间。

8. 发明申请

WO2017112234A1 HARDWARE APPARATUSES AND METHODS FOR MEMORY CORRUPTION DETECTION 审中-公开
标题翻译：硬件设备和记忆腐败检测方法
公开(公告)号：WO2017112234A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063211
申请日：2016-11-22
申请人： INTEL CORPORATION
发明人： STARK, Tomer , GABOR, Ron , NUZMAN, Joseph , SADE, Raanan , BIGBEE, Bryant E.
IPC分类号： G06F12/02 , G06F11/07
CPC分类号： G06F11/079 , G06F9/38 , G06F11/073 , G06F11/0751 , G06F12/00
摘要： Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
摘要翻译：描述与存储器损坏检测有关的方法和设备。在一个实施例中，硬件处理器包括执行单元和存储器管理单元，所述执行单元执行指令以请求访问存储器的块，所述指针指向存储器的块，以及存储器管理单元，指针中的存储器损坏检测值用该存储器中用于该块的存储器损坏检测值进行验证，其中指针中存储器损坏检测值的位置可在第一位置和第二不同位置之间选择。

9. 发明申请

WO2016193774A1 MULTI-CORE PROCESSOR FOR EXECUTION OF STRANDS OF INSTRUCTIONS GROUPED ACCORDING TO CRITICALITY 审中-公开
标题翻译：用于执行根据关键性分组的指令的多核处理器
公开(公告)号：WO2016193774A1
公开(公告)日：2016-12-08
申请号：PCT/IB2015/001148
申请日：2015-06-01
申请人： INTEL CORPORATION
发明人： TITOV, Alexandr , MASLENNIKOV, Dmitry , SHISHLOV, Sergey , SCHERBININ, Sergey , BUROV, Valentin , GABOR, Ron , MOTIN, Denis , SHIMKO, Oleg , GARIFULLIN, Kamil , BUTUZOV, Alexander , PODKORYTOV, Evgeniy , CHUDNOVETS, Andrey
IPC分类号： G06F9/45 , G06F9/38
CPC分类号： G06F9/38 , G03F1/36 , G03F1/70 , G03F7/0005 , G06F9/30003 , G06F9/3017 , G06F9/3836 , G06F9/3851 , G06F9/3889 , G06F9/44
摘要： In an embodiment, a processor includes a plurality of cores. Each core may include strand logic to, for each strand of a plurality of strands, fetch an instruction group uniquely associated with the strand, wherein the instruction group is one of a plurality of instruction groups, wherein the plurality of instruction groups is obtained by dividing instructions of an application program according to instruction criticality. The strand logic may also be to retire the instruction group in an original order of the application program. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核。每个核心可以包括对于多个线段的每个线段的线逻辑，获取与该线束唯一相关联的指令组，其中指令组是多个指令组中的一个，其中多个指令组是通过划分获得的应用程序的指令根据指令的关键性。股线逻辑也可以以应用程序的原始顺序来退出指令组。描述和要求保护其他实施例。

10. 发明申请

WO2010056511A3 TECHNIQUE FOR PROMOTING EFFICIENT INSTRUCTION FUSION 审中-公开
公开(公告)号：WO2010056511A3
公开(公告)日：2010-05-20
申请号：PCT/US2009/062219
申请日：2009-10-27
申请人： INTEL CORPORATION , OUZIEL, Ido , RAPPOPORT, Lihu , VALENTINE, Robert , GABOR, Ron , RAGHUVANSHI, Pankaj
发明人： OUZIEL, Ido , RAPPOPORT, Lihu , VALENTINE, Robert , GABOR, Ron , RAGHUVANSHI, Pankaj
IPC分类号： G06F9/06 , G06F9/22 , G06F9/30
摘要： A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

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