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1. 发明申请

WO2009120981A2 VECTOR INSTRUCTIONS TO ENABLE EFFICIENT SYNCHRONIZATION AND PARALLEL REDUCTION OPERATIONS 审中-公开
标题翻译：向导说明能够实现高效的同步和并行减少运行
公开(公告)号：WO2009120981A2
公开(公告)日：2009-10-01
申请号：PCT/US2009038596
申请日：2009-03-27
申请人： INTEL CORP , SMELYANSKIY MIKHAIL , KUMAR SANJEEV , KIM DAEHYUN , LEE VICTOR W , NGUYEN ANTHONY D , CHEN YEN-KUANG , HUGHES CHRISTOPHER , KIM CHANGKYU , CHHUGANI JATIN
发明人： SMELYANSKIY MIKHAIL , KUMAR SANJEEV , KIM DAEHYUN , LEE VICTOR W , NGUYEN ANTHONY D , CHEN YEN-KUANG , HUGHES CHRISTOPHER , KIM CHANGKYU , CHHUGANI JATIN
IPC分类号： G06F9/38 , G06F9/445 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3885 , G06K9/6212 , G06T5/40 , H04N1/4074
摘要： In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器可以包括向量单元，用于响应于单个指令对多个数据元素执行操作;以及控制单元，耦合到向量单元，以将数据元素提供给向量单元，其中控制单元将使能响应于在第一掩模下执行的第一向量指令和在第二掩码下执行的第二向量指令，对至少一些数据元素执行的原子向量操作。描述和要求保护其他实施例。

2. 发明申请

WO2006072061A3 SYSTEM AND METHOD FOR NON-UNIFORM CACHE IN A MULTI-CORE PROCESSOR 审中-公开
标题翻译：在多核处理器中进行非均匀高速缓存的系统和方法
公开(公告)号：WO2006072061A3
公开(公告)日：2007-01-18
申请号：PCT/US2005047592
申请日：2005-12-27
申请人： INTEL CORP , HUGHES CHRISTOPHER , TUCK III JAMES , LEE VICTOR , CHEN YEN-KUANG
发明人： HUGHES CHRISTOPHER , TUCK III JAMES , LEE VICTOR , CHEN YEN-KUANG
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0833 , G06F12/0846 , G06F12/0853 , G06F2212/271
摘要： A system and method for the design and operation of a distributed shared cache in a multi-core processor is disclosed. In one embodiment, the shared cache may be distributed among multiple cache molecules. Each of the cache molecules may be closest, in terms of access latency time, to one of the processor cores. In one embodiment, a cache line brought in from memory may initially be placed into a cache molecule that is not closest to a requesting processor core. When the requesting processor core makes repeated accesses to that cache line, it may be moved either between cache molecules or within a cache molecule. Due to the ability to move the cache lines within the cache, in various embodiments special search methods may be used to locate a particular cache line.
摘要翻译：公开了一种用于在多核处理器中设计和操作分布式共享高速缓存的系统和方法。在一个实施例中，共享高速缓存可以分布在多个高速缓存分子之间。每个缓存分子在访问延迟时间方面可能最接近于处理器核心之一。在一个实施例中，从存储器引入的高速缓存行可以最初被放置在不最接近请求处理器核的高速缓存分
区中。当请求处理器核心重复访问该高速缓存行时，其可以在高速缓存分子之间或高速缓存分子内移动。由于能够将高速缓存线移动到高速缓存内，在各种实施例中，可以使用特殊搜索方法来定位特定的高速缓存行。

3. 发明申请

WO2006072064A3 SYSTEM AND METHOD FOR CACHE COHERENCY IN A CACHE WITH DIFFERENT CACHE LOCATION LENGTHS 审中-公开
标题翻译：用于具有不同高速缓存位置长度的高速缓存中的高速缓存一致性的系统和方法
公开(公告)号：WO2006072064A3
公开(公告)日：2006-09-14
申请号：PCT/US2005047595
申请日：2005-12-27
申请人： INTEL CORP , CHEN YEN-KUANG , HUGHES CHRISTOPHER , TUCK III JAMES
发明人： CHEN YEN-KUANG , HUGHES CHRISTOPHER , TUCK III JAMES
IPC分类号： G06F12/04 , G06F12/08
CPC分类号： G06F12/04 , G06F12/0817 , G06F12/0886 , Y10S707/99952
摘要： A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. A state tree may be created from data in a sharing vector. When a request arrives from a level one cache, the level two cache may examine the nodes of the state tree to determine whether the node of the state tree corresponding to the incoming request is already active. The results of this determination may be used to inhibit or permit the concurrent processing of the request.
摘要翻译：公开了一种用于在一级高速缓存中设计和操作具有不同高速缓存位置长度的高速缓存系统的系统和方法。在一个实施例中，每个一级高速缓存可以包括不同长度的高速缓存位置组，其能够保存二级高速缓存线的部分。状态树可以从共享向量中的数据创建。当请求从一级高速缓存到达时，二级高速缓存可以检查状态树的节点以确定与输入请求相对应的状态树的节点是否已经是活动的。该确定的结果可用于禁止或允许请求的并行处理。

4. 发明申请

WO2014051733A3 VECTOR MOVE INSTRUCTION CONTROLLED BY READ AND WRITE MASKS 审中-公开
标题翻译：矢量移动指令由读和写掩码控制
公开(公告)号：WO2014051733A3
公开(公告)日：2014-08-21
申请号：PCT/US2013045429
申请日：2013-06-12
申请人： INTEL CORP
发明人： PLOTNIKOV MIKHAIL , NARAIKIN ANDREY , HUGHES CHRISTOPHER
IPC分类号： G06F9/30 , G06F9/06
CPC分类号： G06F15/8084 , G06F9/3885
摘要： A processor executes a vector move instruction to move data elements from a second vector register to a first vector register under the control of a first mask register and a second mask register. A register file within the processor includes the first vector register, the second vector register, the first mask register and the second mask register. In response to the vector move instruction, execution circuitry in the processor is to replace a given number of target data elements in the first vector register with the given number of source data elements in the second vector register. Each source data element corresponds to a mask bit in the second mask register having a second bit value, and wherein each target data element corresponds to a mask bit in the first mask register having a first bit value.
摘要翻译：处理器在第一掩码寄存器和第二掩码寄存器的控制下执行矢量移动指令以将数据元素从第二矢量寄存器移动到第一矢量寄存器。处理器内的寄存器文件包括第一矢量寄存器，第二矢量寄存器，第一掩码寄存器和第二掩码寄存器。响应于向量移动指令，处理器中的执行电路用第二向量寄存器中的给定数量的源数据元素替换第一向量寄存器中的给定数量的目标数据元素。每个源数据元素对应于具有第二比特值的第二掩码寄存器中的掩码比特，并且其中每个目标数据元素对应于第一掩码寄存器中具有第一比特值的掩码比特。

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