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1. 发明申请

WO2019133052A1 VISUAL FOG 审中-公开
公开(公告)号：WO2019133052A1
公开(公告)日：2019-07-04
申请号：PCT/US2018/040390
申请日：2018-06-29
申请人： YANG, Shao-Wen , CHEN, Yen-Kuang , ALTARAWNEH, Ragaad Mohammed Irsehid , MUNOZ CHIABRANDO, Juan Pablo , CHIN, Siew Wen , DATTA, Kushal , DULLOOR, Subramanya R. , ZAMORA ESQUIVEL, Julio C. , FLOREZ CHOQUE, Omar Ulises , GUPTA, Vishakha , HAHN, Scott D. , ILLIKKAL, Rameshkumar , JAIN, Nilesh Kumar , KAMAROL, Siti Khairuni Amalina , KESHAVAMURTHY, Anil S. , LAU, Heng Kar , LEFMAN, Jonathan A. , LIAO, Yiting , MILLSAP, Michael G. , NDIOUR, Ibrahima J. , REMIS, Luis Carlos Maria , SANJAY, Addicam V. , SARWAR, Usman , SCHOOLER, Eve M. , SMITH, Ned M. , SOMAYAZULU, Vallabhajosyula S. , STRONG, Christina R. , TICKOO, Omesh , VARADARAJAN, Srenivas , VARGAS, Jesús A. Cruz , MOUSTAFA, Hassnaa , RAGHUNATH, Arun , BARTFAI-WALCOTT, Katalin Klara , HYDE, Maruti Gupta , VEMBAR, Deepak S. , MCCARTHY, Jessica
发明人： YANG, Shao-Wen , CHEN, Yen-Kuang , ALTARAWNEH, Ragaad Mohammed Irsehid , MUNOZ CHIABRANDO, Juan Pablo , CHIN, Siew Wen , DATTA, Kushal , DULLOOR, Subramanya R. , ZAMORA ESQUIVEL, Julio C. , FLOREZ CHOQUE, Omar Ulises , GUPTA, Vishakha , HAHN, Scott D. , ILLIKKAL, Rameshkumar , JAIN, Nilesh Kumar , KAMAROL, Siti Khairuni Amalina , KESHAVAMURTHY, Anil S. , LAU, Heng Kar , LEFMAN, Jonathan A. , LIAO, Yiting , MILLSAP, Michael G. , NDIOUR, Ibrahima J. , REMIS, Luis Carlos Maria , SANJAY, Addicam V. , SARWAR, Usman , SCHOOLER, Eve M. , SMITH, Ned M. , SOMAYAZULU, Vallabhajosyula S. , STRONG, Christina R. , TICKOO, Omesh , VARADARAJAN, Srenivas , VARGAS, Jesús A. Cruz , MOUSTAFA, Hassnaa , RAGHUNATH, Arun , BARTFAI-WALCOTT, Katalin Klara , HYDE, Maruti Gupta , VEMBAR, Deepak S. , MCCARTHY, Jessica
IPC分类号： G06T7/11 , G06T1/00
摘要： In one embodiment, an apparatus comprises a processor to: identify a workload comprising a plurality of tasks; generate a workload graph based on the workload, wherein the workload graph comprises information associated with the plurality of tasks; identify a device connectivity graph, wherein the device connectivity graph comprises device connectivity information associated with a plurality of processing devices; identify a privacy policy associated with the workload; identify privacy level information associated with the plurality of processing devices; identify a privacy constraint based on the privacy policy and the privacy level information; and determine a workload schedule, wherein the workload schedule comprises a mapping of the workload onto the plurality of processing devices, and wherein the workload schedule is determined based on the privacy constraint, the workload graph, and the device connectivity graph. The apparatus further comprises a communication interface to send the workload schedule to the plurality of processing devices.

2. 发明申请

WO2017111833A1 REUSABLE DEVICE MANAGEMENT IN MACHINE-TO-MACHINE SYSTEMS 审中-公开
标题翻译：机器对机器系统中可重复使用的设备管理
公开(公告)号：WO2017111833A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000391
申请日：2015-12-26
申请人： INTEL CORPORATION , YANG, Shao-Wen , CHEN, Yen-Kuang
发明人： YANG, Shao-Wen , CHEN, Yen-Kuang
IPC分类号： H04L12/24 , H04L29/08
CPC分类号： H04L67/12 , H04L67/34 , H04W4/70
摘要： A plurality of devices are detected within range of a particular device, and capabilities of each of the plurality of devices are determined, as well as a respective taxonomy to be associated with each device based on the device's capabilities. A set of asset abstractions are identified, referenced by a particular software application configured to manage a particular machine-to-machine network. Each asset abstraction can correspond to a respective one of the set of taxonomies, and the particular machine-to-machine network can be built from an instance of each one of the set of asset abstractions. A subset of the plurality of devices can be selected for deployment in the particular machine-to-machine network based on the associated taxonomies, the subset of devices representing an instance of each one of the set of asset abstractions. The subset of devices are then automatically deployed to implement the instance of the particular machine-to-machine network.
摘要翻译：在特定设备的范围内检测到多个设备，并且确定多个设备中的每一个的能力以及基于设备的能力与每个设备相关联的相应分类法。识别一组资产抽象，由被配置为管理特定机器对机器网络的特定软件应用参考。每个资产抽象可以对应于该组分类中相应的一个，并且该特定机器对机器网络可以从该组资产抽象中的每一个的实例构建。可基于相关联的分类来选择多个设备的子集以用于部署在特定的机器对机器网络中，设备的子集表示该组资产抽象中的每一个的实例。然后自动部署设备的子集以实现特定机器对机器网络的实例。

3. 发明申请

WO2012087583A3 MECHANISM FOR CONFLICT DETECTION USING SIMD 审中-公开
标题翻译：使用SIMD进行冲突检测的机制
公开(公告)号：WO2012087583A3
公开(公告)日：2012-09-27
申请号：PCT/US2011063836
申请日：2011-12-07
申请人： INTEL CORP , SMELYANSKIY MIKHAIL , CHEN YEN-KUANG , KIM DAEHYUN , HUGHES CHRISTOPHER J , LEE VICTOR W
发明人： SMELYANSKIY MIKHAIL , CHEN YEN-KUANG , KIM DAEHYUN , HUGHES CHRISTOPHER J , LEE VICTOR W
IPC分类号： G06F13/16 , G06F15/80
CPC分类号： G06F9/3887 , G06F9/345
摘要： A system and method are configured to detect conflicts when converting scalar processes to parallel processes ("SIMDifying"). Conflicts may be detected for an unordered single index, an ordered single index and/or ordered pairs of indices. Conflicts may be further detected for read-after-write dependencies. Conflict detection is configured to identify operations (i.e., iterations) in a sequence of iterations that may not be done in parallel.
摘要翻译：将系统和方法配置为在将标量过程转换为并行进程（“SIMDifying”）时检测冲突。可以针对无序单索引，有序单索引和/或有序索引对检测冲突。读写依赖关系可能会进一步检测到冲突。冲突检测被配置为识别可能不并行完成的迭代序列中的操作（即迭代）。

4. 发明申请

WO2017052624A1 IOT SERVICE MODELING WITH LAYERED ABSTRACTION FOR REUSABILITY OF APPLICATIONS AND RESOURCES 审中-公开
标题翻译： IOT服务建模与应用和资源的可重用性的层叠抽象
公开(公告)号：WO2017052624A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052361
申请日：2015-09-25
申请人： INTEL CORPORATION , YANG, Shao-Wen , CHEN, Yen-Kuang
发明人： YANG, Shao-Wen , CHEN, Yen-Kuang
IPC分类号： H04L29/08 , H04L12/24
CPC分类号： H04L41/0803 , H04W4/70
摘要： Systems, apparatuses and methods may identify a capability abstraction in a request to configure a first Internet of Things (IOT) application in a physical environment including a plurality of IOT devices and select a resource abstraction from a plurality of resource abstractions based on the capability abstraction. The selected resource abstraction may correspond to a first IOT device in the plurality of IOT devices. Additionally, the first IOT application may be bound with the first IOT device. In one example, first data originating from the first IOT device is received, a first runtime abstraction is selected from a plurality of runtime abstractions, wherein the first runtime abstraction corresponds to the first IOT application, and the first data is sent to the first IOT application via the first runtime abstraction.
摘要翻译：系统，装置和方法可以识别在包括多个IOT设备的物理环境中配置物联网（IOT）应用的请求中的能力抽象，并且基于能力抽象从多个资源抽象中选择资源抽象。所选择的资源抽象可以对应于多个IOT设备中的第一IOT设备。另外，第一IOT应用可以与第一IOT设备绑定。在一个示例中，接收来自第一IOT设备的第一数据，从多个运行时抽象中选择第一运行时抽象，其中第一运行时抽象对应于第一IOT应用，并且第一数据被发送到第一IOT 应用程序通过第一个运行时抽象。

5. 发明申请

WO2012087548A3 VECTOR CONFLICT INSTRUCTIONS 审中-公开
标题翻译：矢量冲突指示
公开(公告)号：WO2012087548A3
公开(公告)日：2012-08-16
申请号：PCT/US2011063307
申请日：2011-12-05
申请人： INTEL CORP , HUGHES CHRISTOPHER J , CHARNEY MARK J , CHEN YEN-KUANG , CORBAL JESUS , FORSYTH ANDREW T , GIRKAR MILIND B , HALL JONATHAN C , IDO HIDEKI , VALENTINE ROBERT , WIEDEMEIER JEFFREY
发明人： HUGHES CHRISTOPHER J , CHARNEY MARK J , CHEN YEN-KUANG , CORBAL JESUS , FORSYTH ANDREW T , GIRKAR MILIND B , HALL JONATHAN C , IDO HIDEKI , VALENTINE ROBERT , WIEDEMEIER JEFFREY
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30043 , G06F9/3838
摘要： A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.
摘要翻译：描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

6. 发明申请

WO2009120981A3 VECTOR INSTRUCTIONS TO ENABLE EFFICIENT SYNCHRONIZATION AND PARALLEL REDUCTION OPERATIONS 审中-公开
公开(公告)号：WO2009120981A3
公开(公告)日：2009-10-01
申请号：PCT/US2009/038596
申请日：2009-03-27
申请人： INTEL CORPORATION , SMELYANSKIY, Mikhail , KUMAR, Sanjeev , KIM, Daehyun , LEE, Victor, W. , NGUYEN, Anthony, D. , CHEN, Yen-Kuang , HUGHES, Christopher , KIM, Changkyu , CHHUGANI, Jatin
发明人： SMELYANSKIY, Mikhail , KUMAR, Sanjeev , KIM, Daehyun , LEE, Victor, W. , NGUYEN, Anthony, D. , CHEN, Yen-Kuang , HUGHES, Christopher , KIM, Changkyu , CHHUGANI, Jatin
IPC分类号： G06F9/38 , G06F9/445 , G06F15/80
摘要： In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.

7. 发明申请

WO2009120981A2 VECTOR INSTRUCTIONS TO ENABLE EFFICIENT SYNCHRONIZATION AND PARALLEL REDUCTION OPERATIONS 审中-公开
标题翻译：向导说明能够实现高效的同步和并行减少运行
公开(公告)号：WO2009120981A2
公开(公告)日：2009-10-01
申请号：PCT/US2009038596
申请日：2009-03-27
申请人： INTEL CORP , SMELYANSKIY MIKHAIL , KUMAR SANJEEV , KIM DAEHYUN , LEE VICTOR W , NGUYEN ANTHONY D , CHEN YEN-KUANG , HUGHES CHRISTOPHER , KIM CHANGKYU , CHHUGANI JATIN
发明人： SMELYANSKIY MIKHAIL , KUMAR SANJEEV , KIM DAEHYUN , LEE VICTOR W , NGUYEN ANTHONY D , CHEN YEN-KUANG , HUGHES CHRISTOPHER , KIM CHANGKYU , CHHUGANI JATIN
IPC分类号： G06F9/38 , G06F9/445 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3885 , G06K9/6212 , G06T5/40 , H04N1/4074
摘要： In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器可以包括向量单元，用于响应于单个指令对多个数据元素执行操作;以及控制单元，耦合到向量单元，以将数据元素提供给向量单元，其中控制单元将使能响应于在第一掩模下执行的第一向量指令和在第二掩码下执行的第二向量指令，对至少一些数据元素执行的原子向量操作。描述和要求保护其他实施例。

8. 发明申请

WO2006072064A2 SYSTEM AND METHOD FOR CACHE COHERENCY IN A CACHE WITH DIFFERENT CACHE LOCATION LENGTHS 审中-公开
标题翻译：在具有不同缓存位置的缓存中进行高速缓存的系统和方法
公开(公告)号：WO2006072064A2
公开(公告)日：2006-07-06
申请号：PCT/US2005/047595
申请日：2005-12-27
申请人： INTEL CORPORATION , CHEN, Yen-kuang , HUGHES, Christopher , TUCK III, James
发明人： CHEN, Yen-kuang , HUGHES, Christopher , TUCK III, James
IPC分类号： G06F12/04 , G06F12/08
CPC分类号： G06F12/04 , G06F12/0817 , G06F12/0886 , Y10S707/99952
摘要： A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. A state tree may be created from data in a sharing vector. When a request arrives from a level one cache, the level two cache may examine the nodes of the state tree to determine whether the node of the state tree corresponding to the incoming request is already active. The results of this determination may be used to inhibit or permit the concurrent processing of the request.
摘要翻译：公开了一种用于在一级缓存中具有不同高速缓存位置长度的缓存系统的设计和操作的系统和方法。在一个实施例中，每个级别一个高速缓存可以包括不同长度的高速缓存位置组，能够保持二级高速缓存行的部分。状态树可以从共享向量中的数据创建。当请求从一级缓存到达时，二级缓存可以检查状态树的节点，以确定与进入请求相对应的状态树的节点是否已经是活动的。该确定的结果可以用于抑制或允许并发处理请求。

9. 发明申请

WO2017052632A1 HETEROGENEOUS DISTRIBUTED RUNTIME CODE THAT SHARES IOT RESOURCES 审中-公开
标题翻译：具有共享资源的异质分布式运行代码
公开(公告)号：WO2017052632A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052387
申请日：2015-09-25
申请人： INTEL CORPORATION , YANG, Shao-Wen , CHEN, Yen-Kuang
发明人： YANG, Shao-Wen , CHEN, Yen-Kuang
IPC分类号： G06F9/445 , G06F9/44
CPC分类号： G06F9/44521 , G06F8/60 , G06F8/71
摘要： Systems, apparatuses and methods may receive, at a local Internet of Things (IOT) device, a request to deploy an IOT application. Additionally, the IOT application may be partitioned into a plurality of atomic nodes, wherein configuration information for the plurality of atomic nodes may be sent, at runtime, to a plurality of remote IOT devices having abstracted resources that support operation of the first plurality of atomic nodes. In one example, the configuration information is sent via a device independent message protocol having a universal namespace.
摘要翻译：系统，设备和方法可以在本地物联网（IOT）设备上接收部署IOT应用的请求。此外，IOT应用可以被划分成多个原子节点，其中用于多个原子节点的配置信息可以在运行时被发送到具有支持第一多个原子的操作的抽象资源的多个远程IOT设备节点。在一个示例中，通过具有通用命名空间的与设备无关的消息协议来发送配置信息。

10. 发明申请

WO2006072061A2 SYSTEM AND METHOD FOR NON-UNIFORM CACHE IN A MULTI-CORE PROCESSOR 审中-公开
标题翻译：在多核处理器中非均匀高速缓存的系统和方法
公开(公告)号：WO2006072061A2
公开(公告)日：2006-07-06
申请号：PCT/US2005/047592
申请日：2005-12-27
申请人： INTEL CORPORATION , HUGHES, Christopher , TUCK III, James , LEE, Victor , CHEN, Yen-kuang
发明人： HUGHES, Christopher , TUCK III, James , LEE, Victor , CHEN, Yen-kuang
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0833 , G06F12/0846 , G06F12/0853 , G06F2212/271
摘要： A system and method for the design and operation of a distributed shared cache in a multi-core processor is disclosed. In one embodiment, the shared cache may be distributed among multiple cache molecules. Each of the cache molecules may be closest, in terms of access latency time, to one of the processor cores. In one embodiment, a cache line brought in from memory may initially be placed into a cache molecule that is not closest to a requesting processor core. When the requesting processor core makes repeated accesses to that cache line, it may be moved either between cache molecules or within a cache molecule. Due to the ability to move the cache lines within the cache, in various embodiments special search methods may be used to locate a particular cache line.
摘要翻译：公开了一种用于在多核处理器中设计和操作分布式共享高速缓存的系统和方法。在一个实施例中，共享高速缓存可以分布在多个高速缓存分子之间。每个缓存分子在接入等待时间方面可能最接近于其中一个处理器核心。在一个实施例中，从存储器引入的高速缓存行可以最初被放置到不最接近请求处理器核的高速缓存分
区中。当请求处理器核心重复访问该高速缓存行时，其可以在高速缓存分子之间或高速缓存分子内移动。由于能够在高速缓存中移动高速缓存线，所以在各种实施例中，可以使用特殊搜索方法来定位特定高速缓存行。

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