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1. 发明申请

WO2011081719A3 PERFORMING MODE SWITCHING IN AN UNBOUNDED TRANSACTIONAL MEMORY (UTM) SYSTEM 审中-公开
标题翻译：在UTF（UTM）系统中执行模式切换
公开(公告)号：WO2011081719A3
公开(公告)日：2011-11-24
申请号：PCT/US2010056172
申请日：2010-11-10
申请人： INTEL CORP , ADL-TABATABAI ALI-REZA , SAHA BRATIN , BASSIN VADIM , SHEAFFER GAD , GRAY JAN , GROVER VINOD , TAILLEFER MARTIN , LEVANONI YOSSI , DETLEFS DAVE , MAGRUDER MIKE , TOLTON MATT
发明人： ADL-TABATABAI ALI-REZA , SAHA BRATIN , BASSIN VADIM , SHEAFFER GAD , GRAY JAN , GROVER VINOD , TAILLEFER MARTIN , LEVANONI YOSSI , DETLEFS DAVE , MAGRUDER MIKE , TOLTON MATT
IPC分类号： G06F13/14 , G06F12/08
CPC分类号： G06F12/0815 , G06F9/467 , G06F11/141
摘要： In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在具有多个事务执行模式的无界事务存储器（UTM）系统中选择开始第一事务的第一事务执行模式的方法。这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件执行的硬件辅助模式以及软件缓冲器，以及在没有事务性硬件的情况下执行的软件事务存储器（STM）模式。如果在STM模式下没有执行等待事务，则可以将第一事务执行模式选择为硬件模式的最高执行模式，否则可以选择较低的执行模式。描述和要求保护其他实施例。

2. 发明申请

WO2011081718A2 MECHANISMS TO ACCELERATE TRANSACTIONS USING BUFFERED STORES 审中-公开
标题翻译：使用缓冲存储加速交易的机制
公开(公告)号：WO2011081718A2
公开(公告)日：2011-07-07
申请号：PCT/US2010056142
申请日：2010-11-10
申请人： INTEL CORP , ADL-TABATABAI ALI-REZA , NI YANG , SAHA BRATIN , CALLAHAN DAVID , BASSIN VADIM , SHEAFFER GAD
发明人： ADL-TABATABAI ALI-REZA , NI YANG , SAHA BRATIN , CALLAHAN DAVID , BASSIN VADIM , SHEAFFER GAD
IPC分类号： G06F9/06 , G06F3/06 , G06F9/22 , G06F9/46
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30087 , G06F9/466 , G06F9/467 , G06F9/52 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/1027 , G06F2212/621
摘要： In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在第一线程中执行事务存储器（TM）事务，缓冲处理器的高速缓冲存储器的第一缓冲器中的数据块以及获取块上的写监控器以在更新第一缓冲器中的块的位置处的数据的相遇时间处获得该块的所有权。描述并要求保护其他实施例。

3. 发明申请

WO2007078538A3 COORDINATING ACCESS TO MEMORY LOCATIONS FOR HARDWARE TRANSACTIONAL MEMORY TRANSACTIONS AND SOFTWARE TRANSACTIONAL MEMORY TRANSACTIONS 审中-公开
标题翻译：协调对硬件交易记录交易和软件交易记录交易的存储位置访问
公开(公告)号：WO2007078538A3
公开(公告)日：2007-08-30
申请号：PCT/US2006046499
申请日：2006-12-05
申请人： INTEL CORP , ADL-TABATABAI ALI-REZA , SAHA BRATIN , HUDSON RICHARD L , AKKARY HAITHAM , RAJWAR RAVI
发明人： ADL-TABATABAI ALI-REZA , SAHA BRATIN , HUDSON RICHARD L , AKKARY HAITHAM , RAJWAR RAVI
IPC分类号： G06F9/52
CPC分类号： G06F9/467 , G06F12/0815 , G06F2212/507
摘要： Provided is a method, system, and program for coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions. A hardware transaction executing in hardware transactional memory initiates a request to access a memory location. A fault is returned to the hardware transaction request in response to an operation by one software transaction executing in a software transactional memory.
摘要翻译：提供了用于协调对硬件事务存储器事务和软件事务存储器事务的存储器位置的访问的方法，系统和程序。在硬件事务存储器中执行的硬件事务启动访问存储器位置的请求。响应于在软件事务存储器中执行的一个软件事务的操作，错误返回到硬件事务请求。

4. 发明申请

WO2007092422A2 HARDWARE ACCELERATION FOR A SOFTWARE TRANSACTIONAL MEMORY SYSTEM 审中-公开
标题翻译：用于软件交易存储系统的硬件加速
公开(公告)号：WO2007092422A2
公开(公告)日：2007-08-16
申请号：PCT/US2007003112
申请日：2007-02-06
申请人： INTEL CORP , SAHA BRATIN , ADL-TABATABAI ALI-REZA , JACOBSON QUINN
发明人： SAHA BRATIN , ADL-TABATABAI ALI-REZA , JACOBSON QUINN
CPC分类号： G06F13/4243 , G06F9/3834 , G06F9/466 , G06F9/526
摘要： A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.
摘要翻译：一种用于加速事务执行的方法和装置。只有在事务中第一次访问共享内存条时，才会调用/执行与事务中的内存访问引用的共享内存条相关联的障碍。提供诸如事务字段/事务位之类的硬件支持来确定访问是否是在事务挂起期间对共享存储器行的第一次访问。另外，在积极的操作模式中，代表存储在共享存储器行中的元素的版本号的版本号在保存验证成本的承诺时不被存储和验证。而且，即使在谨慎的模式下，存储版本号以启用验证，如果在执行交易期间没有发生访问的共享内存条的驱逐，则可能不会产生验证成本。

5. 发明申请

WO2014107143A3 METHOD, APPARATUS, AND SYSTEM FOR ADAPTIVE THREAD SCHEDULING IN TRANSACTIONAL MEMORY SYSTEMS 审中-公开
标题翻译：方法，装置和系统用于自适应线程调度在交互式存储器系统中
公开(公告)号：WO2014107143A3
公开(公告)日：2014-09-25
申请号：PCT/US2012059204
申请日：2012-10-08
申请人： INTEL CORP , LEWIS BRIAN T , SAHA BRATIN
发明人： LEWIS BRIAN T , SAHA BRATIN
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/467 , G06F9/4881
摘要： An apparatus and method is described herein for adaptive thread scheduling in a transactional memory environment. A number of conflicts in a thread over time are tracked. And if the conflicts exceed a threshold, the thread may be delayed (adaptively scheduled) to avoid conflicts between competing threads. Moreover, a more complex version may track a number of transaction aborts within a first thread that are caused by a second thread over a period, as well as a total number of transactions executed by the first thread over the period. From the tracking, a conflict ratio is determined for the first thread with regard to the second thread. And when the first thread is to be scheduled, it may be delayed if the second thread is running and the conflict ratio is over a conflict ratio threshold.
摘要翻译：这里描述了一种在事务存储器环境中的自适应线程调度的装置和方法。跟踪线程中的一些冲突。并且如果冲突超过阈值，线程可能被延迟（自适应调度），以避免竞争线程之间的冲突。此外，更复杂的版本可以跟踪在一段时间内由第二线程引起的第一线程内的多个事务中止以及在该周期上由第一线程执行的事务的总数。从跟踪中，针对第二线程确定第一线程的冲突比。并且当第一个线程被调度时，如果第二个线程正在运行并且冲突比超过了冲突比阈值，它可能被延迟。

6. 发明申请

WO2007130367A2 SYSTEM AND METHOD FOR ALLOCATING AND DEALLOCATING MEMORY WITHIN TRANSACTIONAL CODE 审中-公开
标题翻译：用于在交易代码中分配和分配存储器的系统和方法
公开(公告)号：WO2007130367A2
公开(公告)日：2007-11-15
申请号：PCT/US2007010483
申请日：2007-05-01
申请人： INTEL CORP , HERTZBERG BEN , SAHA BRATIN , ADI-TABATABAI ALI-REZA
发明人： HERTZBERG BEN , SAHA BRATIN , ADI-TABATABAI ALI-REZA
CPC分类号： G06F12/023 , G06F9/466 , G06F9/5016 , Y10S707/99943 , Y10S707/99953
摘要： Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.
摘要翻译：提供了方法和系统，用于在事务代码（包括嵌套事务代码）中管理内存分配和释放。方法和系统通过使用标识符（如序列号）来处理事务中的内存管理来管理事务内存操作。方法和系统还保留在事务中止和提交时间执行的延迟操作的列表。与一个或多个事务相关联的多个存储器管理例程检查当前事务的事务序列号，操纵提交和/或撤销日志，以及设置/使用关联对象的事务序列号，但不限于此。方法和系统在事务代码中提供内存分配和释放，同时保留事务语义。描述和要求保护其他实施例。

7. 发明申请

WO2010056587A3 SHARED VIRTUAL MEMORY 审中-公开
标题翻译：共享的虚拟内存
公开(公告)号：WO2010056587A3
公开(公告)日：2010-08-26
申请号：PCT/US2009063368
申请日：2009-11-05
申请人： INTEL CORP , CHEN HU , GAO YING , XIAOCHENG ZHOU , YAN SHOUMENG , ZHANG PEINAN , RAJAGOPALAN MOHAN , FANG JESSE , MENDELSON AVI , SAHA BRATIN
发明人： CHEN HU , GAO YING , XIAOCHENG ZHOU , YAN SHOUMENG , ZHANG PEINAN , FANG JESSE , MENDELSON AVI , SAHA BRATIN
IPC分类号： G06F15/167 , G06F9/46 , G06F13/14
CPC分类号： G06F9/544 , G06F12/0815 , G06F12/084 , G06F12/1009 , G06F12/1063 , G06F12/1072 , G06F12/1081 , G06F12/109 , G06F2212/161 , G06F2212/622 , G06F2212/656 , G06F2212/657 , G06F2212/682 , G06T1/20 , G06T1/60
摘要： Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.
摘要翻译：本发明的实施例提供了一种用于CPU-GPU平台的编程模型。特别地，本发明的实施例为集成和分立设备提供统一的编程模型。该模型还适用于多个GPU卡和混合GPU系统（分立和集成）。这允许软件供应商编写单个应用程序堆栈并将其定位到所有不同的平台。另外，本发明的实施例提供了CPU和GPU之间的共享存储器模型。而不是共享整个虚拟地址空间，只需要共享虚拟地址空间的一部分。这允许在离散和集成设置中有效实现。

8. 发明申请

WO2006012103A2 METHOD AND APPARATUS FOR SPECULATIVE EXECUTION OF UNCONTENDED LOCK INSTRUCTIONS 审中-公开
标题翻译：用于未执行的锁定指令的执行的方法和装置
公开(公告)号：WO2006012103A2
公开(公告)日：2006-02-02
申请号：PCT/US2005021838
申请日：2005-06-17
申请人： INTEL CORP , SAHA BRATIN , MERTEN MATTHEW C , HAMMARLUND PER
发明人： SAHA BRATIN , MERTEN MATTHEW C , HAMMARLUND PER
IPC分类号： G06F9/00
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3842
摘要： A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.
摘要翻译：公开了一种在无序处理器中推测性地执行锁定指令的方法和设备。在一个实施例中，预测给定的锁定指令是否实际上将被争用。如果不是，则锁定指令可被视为具有可被推测执行的正常加载微操作。监视逻辑可以查找锁指令实际上是否存在争用的指示。如果没有找到这样的指示，则可以撤销对应于锁定指令的推测加载微操作和其他微操作。但是，如果实际上发现了这样的指示，那么可以重新开始锁定指令，并且可以更新预测机制。

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