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1. 发明申请

WO2016190928A2 SPIKE DOMAIN CONVOLUTION CIRCUIT 审中-公开
标题翻译： SPIKE域转换电路
公开(公告)号：WO2016190928A2
公开(公告)日：2016-12-01
申请号：PCT/US2016/017895
申请日：2016-02-12
申请人： HRL LABORATORIES, LLC
发明人： CRUZ-ALBRECHT, Jose , YUNG, Michael, W. , SRINIVASA, Narayan
IPC分类号： G06T7/00 , G06T9/00
CPC分类号： G06T5/20
摘要： A convolution circuit includes: a plurality of input oscillators, each configured to: receive a corresponding analog input signal of a plurality of analog input signals; and output a corresponding spiking signal of a plurality of spiking signals, the corresponding spiking signal having a spiking rate in accordance with a magnitude of the corresponding analog input signal; a plurality of 1-bit DACs, each of the 1-bit DACs being configured to: receive the corresponding spiking signal of the plurality of spiking signals from a corresponding one of the input oscillators; and receive a corresponding weight of a convolution kernel comprising a plurality of weights; output a corresponding weighted output of a plurality of weighted outputs in accordance with the corresponding spiking signal and the corresponding weight; and an output oscillator configured to generate an output spike signal in accordance with the plurality of weighted outputs from the plurality of 1-bit DACs.
摘要翻译：卷积电路包括：多个输入振荡器，每个输入振荡器被配置为：接收多个模拟输入信号的对应的模拟输入信号; 并输出多个尖峰信号的对应尖峰信号，相应的尖峰信号具有根据对应的模拟输入信号的大小的尖峰速率; 多个1位DAC，所述1位DAC中的每一个被配置为：从所述输入振荡器中的相应一个接收所述多个尖峰信号的对应尖峰信号; 并且接收包括多个权重的卷积核的相应权重; 根据相应的加标信号和相应的权重输出多个加权输出的对应加权输出; 以及输出振荡器，被配置为根据来自所述多个1位DAC的所述多个加权输出生成输出尖峰信号。

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