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1. 发明申请

WO2013165349A1 PROCESSOR PROVIDING MULTIPLE SYSTEM IMAGES 审中-公开
标题翻译：处理器提供多个系统图像
公开(公告)号：WO2013165349A1
公开(公告)日：2013-11-07
申请号：PCT/US2012/035782
申请日：2012-04-30
申请人： HEWLETT PACKARD DEVELOPMENT COMPANY, L.P. , LESARTRE, Gregg , NGUYEN, Vincent , KNEBEL, Patrick
发明人： LESARTRE, Gregg , NGUYEN, Vincent , KNEBEL, Patrick
IPC分类号： G06F15/80 , G06F9/46
CPC分类号： G06F9/4403 , G06F9/44505 , G06F9/45541 , G06F9/45558 , G06F9/5077 , G06F2009/45579 , Y02D10/22 , Y02D10/36
摘要： An example processor includes a plurality of processing core components, one or more memory interface components, and a management component, wherein the one or more memory interface components are each shared by the plurality of processing core components, and wherein the management component is configured to assign each of the plurality of processing core components to one of a plurality of system images.
摘要翻译：示例性处理器包括多个处理核心组件，一个或多个存储器接口组件和管理组件，其中所述一个或多个存储器接口组件各自由所述多个处理核心组件共享，并且其中所述管理组件被配置为将多个处理核心组件中的每一个分配给多个系统映像之一。

2. 发明申请

WO2013165347A1 ADDRESS TRANSLATION GASKET 审中-公开
标题翻译：地址翻译垫
公开(公告)号：WO2013165347A1
公开(公告)日：2013-11-07
申请号：PCT/US2012/035776
申请日：2012-04-30
申请人： HEWLETT PACKARD DEVELOPMENT COMPANY, L.P. , LESARTRE, Gregg , NGUYEN, Vincent , KNEBEL, Patrick
发明人： LESARTRE, Gregg , NGUYEN, Vincent , KNEBEL, Patrick
IPC分类号： G06F15/80 , G06F12/02
CPC分类号： G06F12/06 , G06F12/0284 , G06F12/0292 , G06F12/145 , G06F2212/251
摘要： An example processor includes a plurality of processor core components, a memory interface component, and an address translation gasket. Each processor core component is assigned to one of a plurality of system images, and the plurality of system images share a common memory component by at least utilizing the address translation gasket to maintain separation between memory regions assigned to each of the plurality of system images. The memory interface component is shared by the plurality of independent system images. The address translation gasket is configured to intercept transactions bound for the memory interface component comprising a system image identifier and a target address, generate a translation address based at least in part on the system identifier and the target address, and send the translation address to the memory interface component.
摘要翻译：示例处理器包括多个处理器核心部件，存储器接口部件和地址转换垫圈。每个处理器核心组件被分配给多个系统图像中的一个，并且多个系统图像通过至少利用地址转换垫圈来保持分配给多个系统图像中的每一个的存储器区域之间的分离来共享公共存储器组件。存储器接口组件由多个独立系统映像共享。地址翻译垫圈被配置为截取包括系统图像标识符和目标地址的存储器接口部件绑定的事务，至少部分地基于系统标识符和目标地址生成翻译地址，并将翻译地址发送到内存接口组件。

3. 发明申请

WO2015116203A1 ENCODED CROSS-POINT ARRAY 审中-公开
标题翻译：编码交叉点阵列
公开(公告)号：WO2015116203A1
公开(公告)日：2015-08-06
申请号：PCT/US2014/014272
申请日：2014-01-31
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： LESARTRE, Gregg , GIBSON, Gary , ORDENTLICH, Erik , JEON, Yoocharn
IPC分类号： H04N19/00
CPC分类号： G11C13/003 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2213/77 , H01L27/2463
摘要： A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.
摘要翻译：一种设备包括交叉点阵列和访问电路，以访问分别对应于编码的数据块的存储器元件的子集。对于存储器元件的每个子集，包括子集中的第一存储器元件和该子集中的第二存储器元件的交叉点阵列的行或列还包括位于第一和第二存储器元件之间的第三存储器元件沿着行或列的存储器元件，并且在对应于另一编码块的子集之一中。

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