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1. 发明申请

WO2004095459A3 MAGNETORESISTIVE RAM DEVICE AND METHODS FOR FABRICATING 审中-公开
标题翻译：磁性RAM设备和制造方法
公开(公告)号：WO2004095459A3
公开(公告)日：2005-03-24
申请号：PCT/US2004011864
申请日：2004-04-16
申请人： FREESCALE SEMICONDUCTOR INC , GRYNKEWICH GREGORY , DEHERRERA MARK , DURLAM MARK A , TRACY CLARENCE J
发明人： GRYNKEWICH GREGORY , DEHERRERA MARK , DURLAM MARK A , TRACY CLARENCE J
IPC分类号： G11C20060101 , G11C8/02 , H01L21/00 , H01L21/8246 , H01L27/22 , H01L29/00 , H01L29/82
CPC分类号： H01L27/228 , B82Y10/00
摘要： A method for fabricating an MRAM device structure (10) includes providing a substrate (12) on which is formed a first transistor (14) and a second transistor (14). An operative memory element device (60) is formed in electrical contact with the first transistor (14). At least a portion of a false memory element device (58) is formed in electrical contact with the second transistor (14). A first dielectric layer (62) is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via (66) to the at least a portion of a false memory element device (58) and a second via (64) to the operative memory element device (60). An electrically conductive interconnect layer (68) is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device (58) to the operative memory element device (64).
摘要翻译：一种用于制造MRAM器件结构（10）的方法包括提供其上形成有第一晶体管（14）和第二晶体管（14）的衬底（12）。操作存储元件装置（60）形成为与第一晶体管（14）电接触。伪存储元件器件（58）的至少一部分形成为与第二晶体管（14）电接触。第一介电层（62）沉积在伪存储元件装置和操作存储元件装置的至少一部分上。第一介电层被蚀刻以同时形成第一通孔（66）到伪存储元件器件（58）的至少一部分和第二通孔（64）到操作存储元件器件（60）。沉积导电互连层（68），使得导电互连层从假存储元件装置（58）的至少一部分延伸到可操作存储元件装置（64）。

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