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1. 发明申请

WO2007052091A1 METHOD AND SYSTEM FOR CLOCK SKEW REDUCTION IN CLOCK TREES 审中-公开
标题翻译：时钟中时钟减少的方法和系统
公开(公告)号：WO2007052091A1
公开(公告)日：2007-05-10
申请号：PCT/IB2005/053582
申请日：2005-11-02
申请人： FREESCALE SEMICONDUCTOR, INC. , KUZMIN, Dan , PRIEL, Michael , ZIMIN, Michael
发明人： KUZMIN, Dan , PRIEL, Michael , ZIMIN, Michael
IPC分类号： G06F1/10
CPC分类号： G06F17/5045 , G06F1/10
摘要： A system (200) that includes a clock tree (210) and multiple variable delay components (220). The system (200) is characterized by including a first set of fuses (230) indicative of identities of variable delay components that belong to a first set of variable delay components (240), a second set of fuses (235) indicative of delay values of the variable delay components that belong to the first set of variable delay components (240), and a second set of variable delay components (245) that are set to at least one default delay value. A method (100) for reducing clock skews, the method includes providing (110) a clock tree that includes a set of variable delay components. The method (100) is characterized by selecting (130) a first set of variable delay components in view of timing violations occurring due clock skews, setting (140) delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting (150) delay values of variable delay components that form a second set of variable delay components to at least one default value.
摘要翻译：一种包括时钟树（210）和多个可变延迟组件（220）的系统（200）。系统（200）的特征在于包括第一组熔丝（230），其指示属于第一组可变延迟部件（240）的可变延迟部件的标识，第二组熔丝（235），指示延迟值属于第一组可变延迟分量（240）的可变延迟分量，以及被设置为至少一个默认延迟值的第二组可变延迟分量（245）。一种用于减少时钟偏差的方法（100），所述方法包括提供（110）包括一组可变延迟分量的时钟树。方法（100）的特征在于，考虑到由时钟偏差引起的定时违规，选择（130）第一组可变延迟分量，通过编程设置（140）形成第一组可变延迟分量的可变延迟分量的延迟值将形成第二组可变延迟分量的可变延迟分量的（150）延迟值设置为至少一个默认值。

2. 发明申请

WO2006058559A1 APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION USING SELECTIVE POWER GATING 审中-公开
标题翻译：使用选择功率增益降低功耗的装置和方法
公开(公告)号：WO2006058559A1
公开(公告)日：2006-06-08
申请号：PCT/EP2004/014917
申请日：2004-11-30
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , ZIMIN, Michael
发明人： PRIEL, Michael , KUZMIN, Dan , ZIMIN, Michael
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： A method (200) for reducing power consumption of transistor-based circuit, the method including receiving (230) a low power mode indication; determining (240) whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing (250) power to at least a portion of the transistor-based circuit. An apparatus (200) for reducing power consumption of a transistor-based circuit (100), the apparatus being connected to the transistor-based circuit, and being adapted to receive a low power mode indication, wherein the apparatus includes: means (38) for determining whether to supply power to at least a portion of the transistor-based circuit in response a state of the transistor-based circuit prior the receiving of the low power mode indication; and means for power gating (40, 42), adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination.
摘要翻译：一种用于降低基于晶体管的电路的功耗的方法（200），该方法包括接收（230）低功率模式指示; 确定（240）是否响应于基于晶体管的电路的复位值和在接收到低功率模式指示之前的基于晶体管的电路的状态来向基于晶体管的电路的至少一部分供电，以及选择性地向所述基于晶体管的电路的至少一部分提供（250）功率。一种用于降低基于晶体管的电路（100）的功耗的装置（200），所述装置连接到基于晶体管的电路，并且适于接收低功率模式指示，其中所述装置包括：装置（38）用于在接收到低功率模式指示之前响应于基于晶体管的电路的状态来确定是否向所述基于晶体管的电路的至少一部分供电; 以及用于电源门控（40,42）的装置，适于响应于所述确定而选择性地向所述基于晶体管的电路的至少一部分提供电力。

3. 发明申请

WO2008154127A1 ONE TIME PROGRAMMABLE ELEMENT SYSTEM IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：一体化电路中的一次可编程元件系统
公开(公告)号：WO2008154127A1
公开(公告)日：2008-12-18
申请号：PCT/US2008/064111
申请日：2008-05-19
申请人： FREESCALE SEMICONDUCTOR INC. , KENKARE, Prashant U. , ZIMIN, Michael
发明人： KENKARE, Prashant U. , ZIMIN, Michael
IPC分类号： G11C16/34
CPC分类号： G11C17/16 , G11C17/18
摘要： A system with a repairable memory array (301) having redundant memory cells to replace one or more defective memory cells that are detected after fabrication. The system also includes non memory array circuits having circuitry that may adjust one or more operating parameters such as operating current, operating voltage, resistance, capacitance, timing characteristics and an operating mode. A set of one time programmable elements (105) can be used to selectively store information for modifying operating parameters and replacing the defective memory cells with redundant memory cells.
摘要翻译：具有可修复存储器阵列（301）的系统具有冗余存储器单元以替代在制造之后检测到的一个或多个缺陷存储器单元。该系统还包括具有可调节一个或多个操作参数（例如工作电流，工作电压，电阻，电容，时序特性和操作模式）的电路的非存储器阵列电路。可以使用一组一次性可编程元件（105）来选择性地存储用于修改操作参数的信息和用冗余存储器单元替换有缺陷的存储器单元。

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